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Circuit Implementation of Modular Adders in Custom CMOS VLSI and FPGA

Russian Microelectronics 2023年第7期52卷 648-658页

作者： Bibilo, P.N. Kirienko, N.A. United Institute of Informatics Problems National Academy of Sciences of Belarus Minsk220012 Belarus

Abstract—: Modular arithmetic is often used to create high-speed computing systems based on both custom digital VLSI circuits and field-programmable gate arrays (FPGAs). The problems of hardware implementation of neural networks based on modular arithmetic calculations are relevant today. In this study, the problem of implementing modular adders in the library for designing custom CMOS VLSI systems and FPGAs is considered. Systems of both fully and incompletely defined (partial) Boolean functions, as well as algorithmic descriptions in the VHDL language, are used as the initial descriptions of modular adders. Logical optimization preceding logical synthesis is carried out in the class of disjunctive normal forms, Reed–Muller polynomial representations, and representations of Boolean function systems by binary decision diagrams. Nine experiments are carried out on the efficiency of applying logic optimization in the circuit implementation of modular adders in the library for designing custom CMOS VLSI circuits and FPGAs. The obtained circuits of modular adders for CMOS VLSI systems are estimated by area (total number of transistors), delay, and power consumption;and for FPGAs, by the number of programmable logic elements and power consumption. The experimental results show that the use of partial function models and preliminary logical optimization based on binary decision diagrams makes it possible to obtain modular adders characterized by lower delay values. Algorithmic VHDL models make it possible to obtain CMOS modular adder circuits with a smaller area and lower power consumption. © Pleiades Publishing, Ltd. 2023. ISSN 1063-7397, Russian Microelectronics, 2023, Vol. 52, No. 7, pp. 648–658. Pleiades Publishing, Ltd., 2023. Russian Text The Author(s), 2022, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2022, Vol. 27, No. 4, pp. 489–505.

关键词： Boolean functions

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Fault-Tolerant Self-Timed Counters

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Russian Microelectronics 2024年第8期53卷 798-802页

作者： Zatsarinny, A.A. Stepchenkov, Yu. A. Diachenko, Yu. G. Khilko, D.V. Orlov, G.A. Diachenko, D. Yu. Institute of Informatics Problems Federal Research Center "Computer Science and Control" of Russian Academy of Sciences Moscow119333 Russia

Abstract: The article studies the fault-tolerant self-timed (ST) counter design problem. Combinational ST circuits have a higher fault tolerance in comparison with synchronous counterparts due to redundant information coding and mandatory acknowledgment of all initiated circuit cells’ switch completion. Sequential ST circuits, including counters, are more sensitive to soft errors because a soft error can change a state stored by their memory cells. For their fault-tolerant implementation, special circuitry methods, namely DICE and Quatro, are used. They are similar to the data processing channel duplication, but use transistor cross-connection in the circuit cells. This approach significantly reduces the likelihood of a change in the counter bit’s state due to a soft error. The article proposes DICE-type and Quatro-type ST counter cases, compares their features, and resumes recommendations for the fault-tolerant ST counter implementation. © Pleiades Publishing, Ltd. 2024.

关键词： Combinatorial circuits

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Self-Timed Counter Synthesis

Self-Timed Counter Synthesis

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2024 International Conference on Industrial Engineering, Applications and Manufacturing, ICIEAM 2024

作者： Diachenko, Yuri Stepchenkov, Yuri Khilko, Dmitri Institute Of Informatics Problems Federal Research Center 'Computer Science And Control' Moscow Russia

ISBN: (纸本)9798350395013

Self-timed (ST) circuits have higher reliability in comparison with synchronous counterparts and can serve as a promising circuitry basis for microelectronic control unit implementations for robotic complexes and production systems. However, designing ST circuits is more labor-intensive and non-trivial because of the need to adhere to strict signal generation discipline and build an additional indication subcircuit. The synthesis of combinational ST circuits is quite simply formalized by means of dualizing the logical function system obtained by a logic synthesizer and adding an indication subcircuit. However, when synthesizing ST units with memory, including ST counters, this approach leads to excessive hardware redundancy and, as a consequence, to the resulting solution's low level of performance and soft error tolerance. The article analyzes the circuitry basis for the optimal multi-bit ST counter implementation and proposes a method for synthesizing ST counters based on parameterized templates of the ST counter body and its environment, ensuring self-timed implementation, its full functional compliance with the original description, and close to optimal consumer characteristics. © 2024 IEEE.

关键词： Microelectronics

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Failure-Tolerant Self-Timed Circuits

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Russian Microelectronics 2023年第8期52卷 793-797页

作者： Zatsarinny, A.A. Stepchenkov, Yu. A. Diachenko, Yu. G. Rogdestvenski, Yu. V. Plekhanov, L.P. Institute of Informatics Problems Federal Research Center "Computer Science and Control" of Russian Academy of Sciences Moscow119333 Russia

Abstract: The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to failures. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to soft errors than synchronous counterparts. Duplicating ST channels instead of tripling reduces the failure-tolerant ST circuit’s hardware redundancy and retains its reliability in higher level compared to synchronous counterparts. © Pleiades Publishing, Ltd. 2023.

关键词： Timing circuits

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On One Model of Freezing Biological Living Tissues

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Journal of Mathematical Sciences (United States) 2025年第1期288卷 12-16页

作者： Buzdov, B.K. Institute of Informatics and Regional Management Problems Kabardino-Balkarian Scientific Center of the Russian Academy of Sciences Nalchik Russian Federation

In this paper, we present a new mathematical model of freezing a living biological tissue by a rectangular cryoapplicator and a method for its numerical study based on the use of local one-dimensional difference schemes. The model is a three-dimensional three-phase boundary-value Stefantype problem and has applications in cryosurgery. A special nonlinear dependence of heat sources on the unknown temperature field allows one to take into account the spatial effect of heat localization. © The Author(s), under exclusive licence to Springer Nature Switzerland AG 2025.

关键词： 97M60 cryobiology cryomedicine mathematical modeling Stefan problem

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On the Complexity of the Sequential Sampling Method

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Journal of Applied and Industrial Mathematics 2024年第2期18卷 227-233页

作者： Fomichev, V.M. Security Code LLC Moscow115230 Russia Institute of Informatics Problems of the Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences Moscow119333 Russia

Abstract: A system of Boolean equations can be solved by a sequential sampling method using an-step algorithm, where at theth step the values of all variables essential for the first equations are sampled and false solutions are rejected based on theright-hand sides of the equations,. The estimate of the complexity of the method depends on the structure ofthe sets of essential variables of the equations and attains its minimum after some permutation ofthe system equations. For the optimal permutation of equations we propose an algorithm thatminimizes the average computational complexity of the algorithm under natural probabilisticassumptions. In a number of cases, the construction of such a permutation is computationallydifficult;in this connection, other permutations are proposed which are computed in a simpler waybut may lead to nonoptimal estimates of the complexity of the method. The results implyconditions under which the sequential sampling method degenerates into the exhaustive searchmethod. An example of constructing an optimal permutation is given. © Pleiades Publishing, Ltd. 2024.

关键词： Boolean functions

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Superimposed Root Locus Portraits for Parametric Synthesis of Robust Control Systems 4

Superimposed Root Locus Portraits for Parametric Synthesis o...

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4th IEEE International Conference on Electrical, Computer, and Energy Technologies, ICECET 2024

作者： Nesenchuk, Alla United Institute of Informatics Problems of the Belarusian National Academy of Sciences Digital Transformation Department Minsk Belarus

ISBN: (纸本)9798350395914

Mechatronic devices and equipment, such as electric drives, cutting tools, robots, etc., often operate in conditions of uncertainty, which leads to the lack of their control systems robustness and thus to degradation of their dynamic characteristics. The paper represents a method for robust automatic control system parametric synthesis, considering that two physical parameters are variable (uncertain)s. Mathematical model of the dynamic system is defined in the form of the root locus portrait (root locus) with two physical parameters variation within infinite intervals of their real values (interval parametric uncertainty). A notion of the system 'superimposed root locus' ('superimposed root locus portrait') has been introduced, which is used for calculation of the parameters' values ensuring the dynamic system robust stability. Two different approaches are proposed for the task solution: the first one relies on the extended free root locus application and the second one - on the regular root loci application. Graphical root locus portraits are considered to illustrate the system response to plant parameters' variation. © 2024 IEEE.

关键词： Root loci

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Synthesis of Self-Timed Circuits with Memory

Synthesis of Self-Timed Circuits with Memory

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2024 International Russian Smart Industry Conference, SmartIndustryCon 2024

作者： Sokolov, Igor Stepchenkov, Yuri Diachenko, Yuri Moscow Russia Institute of Informatics Problems of Frc 'Computer Science and Control' of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9798350395044

Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of information and a two-phase operating discipline, which makes it possible to detect the successful circuit switching completion in each phase. The combinational ST circuit synthesis has been well studied, formalized, and implemented in several existing computer-aided design systems for asynchronous digital units. It is based on dualizing the logical function system in order to convert single information signals into dual-rail signals with a null or unit spacer and supplementing an additional indication subcircuit that detects the completion of ST circuit switching into the current phase. The synthesis of ST circuits with memory is less amenable to formalization. The paper considers the problem of implementing typical ST units with memory, namely latches and flip-flops. It analyzes ST latch and flip-flop implementation features and their interaction with the combinational environment, which requires dual-rail coding of information signals, and offers effective circuit solutions that ensure the adequacy of their behavior in relation to synchronous counterparts. © 2024 IEEE.

关键词： Flip flop circuits

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Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit

Desynchronization of a Synchronous Circuit to Synthesize Sel...

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2024 Conference of Young Researchers in Electrical and Electronic Engineering, ElCon 2024

作者： Khilko, Dmitry V. Stepchenkov, Yuri A. Orlov, Georgy A. Grigoriev, Artem A. Diachenko, Yuri G. Institute of Informatics Problems Federal Research Center 'Computer Science and Control' of the Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9798350360646

Within the article the issue of automatic synthesis of self-timed circuits from the original synchronous description in the Verilog language is covered. The key stage in the synthesis of a self-timed circuit is the procedure that identifies the circuit pipeline organization followed by desynchronization. The essence of desynchronization is to replace the global clock signal with a set of request-response interaction signals between functional blocks within an interstage pipeline. This method uses the open source Yosys synthesis toolkit to transform the original behavioral description into a set of logical equations and library elements. The resulting set is subjected to a desynchronization procedure and is formed as a task for further synthesis of a self-timed circuit in the Verilog language. In this case, indication of the end of transient processes is implemented both in combinational and memory circuits. © 2024 IEEE.

关键词： ANTLR desynchronization logic synthesis self-timed circuits Yosys

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Self-Timed Trigger Synthesis with Composite Write-Enable Input

Self-Timed Trigger Synthesis with Composite Write-Enable Inp...

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2024 Conference of Young Researchers in Electrical and Electronic Engineering, ElCon 2024

作者： Stepchenkov, Yuri A. Diachenko, Yuri G. Khilko, Dmitri V. Morozov, Nikolai V. Berstnev, Sergey V. Stepchenkov, Dmitri Y. Institute of Informatics Problems Federal Research Center 'Computer Science and Control' of the Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9798350360646

The article analyzes the correct implementation problem for self-timed latches and flip-flops with a composite write-enable input. Latch and flip-flop circuit implementation cases are described depending on the type of self-timed coding of input signals. A software tool verifying digital circuits on self-timing proves the proposed circuitry solution's correctness. © 2024 IEEE.

关键词： complexity flip-flop implementation indication latch self-timed circuit

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