This paper deals with one of the potential applications of distribution static compensator (DSTATCOM) to industrial systems for mitigation of voltage dip problem. The dip in voltage is generally encountered during the...
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This paper deals with one of the potential applications of distribution static compensator (DSTATCOM) to industrial systems for mitigation of voltage dip problem. The dip in voltage is generally encountered during the starting of an induction motor. Isolated distribution systems are comparatively not as stiff as grid systems; so large starting currents and objectionable voltage drop during starting of an induction motor could be critical for the entire system. DSTATCOM is one effective solution for isolated power systems facing such power quality problems. The model of DSTATCOM connected in shunt configuration to such an isolated system (3phase, 42.5 kVA alternator) feeding dynamic motor loads is developed using Simulink and PSB of MATLAB software. Simulated results demonstrate that DSTATCOM can be a considered as a viable solution for solving such voltage dip problems
This paper focuses on power quality improvement with DSTATCOM on a small, isolated 42.5 kVA alternator feeding a three-phase, three-wire distribution system. Some power quality aspects like power-factor correction, vo...
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This paper deals with a DSTATCOM (Distribution Static Compensator) for load balancing, neutral current elimination, power factor correction and voltage regulation in three-phase, four-wire distribution system feeding ...
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This paper deals with a DSTATCOM (distribution static compensator) for load balancing, neutral current elimination, power factor correction and voltage regulation in three-phase, four-wire distribution system feeding ...
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This paper deals with a DSTATCOM (distribution static compensator) for load balancing, neutral current elimination, power factor correction and voltage regulation in three-phase, four-wire distribution system feeding commercial and domestic consumers. A four leg voltage source inverter (VSI) configuration with a DC bus capacitor is employed as DSTATCOM. The modified instantaneous reactive power theory (IRPT) is used in the control of DSTATCOM. The capability of the DSTATCOM is demonstrated through results obtained using MATLAB based developed model of the system at different types of loads.
This paper focuses on power quality improvement with DSTATCOM on a small, isolated 42.5 kVA alternator feeding a three-phase, three-wire distribution system. Some power quality aspects like power-factor correction, vo...
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This paper focuses on power quality improvement with DSTATCOM on a small, isolated 42.5 kVA alternator feeding a three-phase, three-wire distribution system. Some power quality aspects like power-factor correction, voltage regulation and load balancing of linear load are discussed and implemented using DSTATCOM. DSTATCOM is realized using a three leg IGBT based PWM-VSI bridge having a DC bus capacitor. A hysteresis rule based carrier-less PWM current controller is used to derive gating pulses for the IGBT switches. The models are developed and simulated in MATLAB using Simulink and Power System Blockset (PSB) toolboxes. It is observed that DSTATCOM is effective in compensating reactive power and improving the power quality of the distribution system
The multi-core architecture has revolutionized the parallel computing. Despite this, the modern age compilers have a long way to achieve auto-parallelization. Through this paper, we introduce a language that encouragi...
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The multi-core architecture has revolutionized the parallel computing. Despite this, the modern age compilers have a long way to achieve auto-parallelization. Through this paper, we introduce a language that encouraging the auto-parallelization. We are also introducing Front-End for our auto-parallelizing compiler. Later, we examined our compiler employing a different number of core and verify results based on different metrics based on total compilation time, memory utilization, power utilization and CPU utilization. At last, we learned that parallelizing multiple files engage more CPU resources, memory and energy, but it finishes the task at hand in less time. In this paper, we have proposed a loop code generation technique that makes the generation of nested loop IR code faster by dividing the blocks into some extra code blocks using a modular approach. Our TAM compiler technique speedup by 7.506, 5.283 and 2.509 against sequential compilation when we utilized 8, 4 and 2 cores respectively. We observed that the CPU utilization of the TAM compiler reaches the maximum permissible limit when an optimal parallelizable instance is compiled.
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