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Correcting on-chip distortion of control pulses with silicon spin qubits

Chinese Physics B 2025年第1期34卷 265-271页

作者： Ming Ni Rong-Long Ma Zhen-Zhen Kong Ning Chu Wei-Zhu Liao Sheng-Kai Zhu Chu Wang Gang Luo Di Liu Gang Cao Gui-Lei Wang Hai-Ou Li Guo-Ping Guo CAS Key Laboratory of Quantum Information University of Science and Technology of China(USTC)Hefei 230026China CAS Center for Excellence in Quantum Information and Quantum Physics University of Science and Technology of ChinaHefei 230026China Integrated Circuit Advanced Process Research and Development Center Institute of MicroelectronicsChinese Academy of Sciences(CAS)Beijing 100029China Hefei National Laboratory Hefei 230088China Beijing Superstring Academy of Memory Technology Beijing 100176China Origin Quantum Computing Company Limited Hefei 230026China

In semiconductor quantum dot systems,pulse distortion is a significant source of coherent errors,which impedes qubit characterization and ***,we demonstrate two calibration methods using a two-qubit system as the detector to correct distortion and calibrate the transfer function of the control *** methods are straightforward to implement,robust against noise,and applicable to a wide range of qubit *** two methods differ in correction accuracy and *** first,coarse predistortion(CPD)method,partially mitigates *** second,all predistortion(APD)method,measures the transfer function and significantly enhances exchange oscillation *** methods use exchange oscillation homogeneity as the metric and are suitable for any qubit driven by a diabatic *** believe these methods will enhance qubit characterization accuracy and operation quality in future applications.

关键词： quantum computation quantum dot pulse distortion

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Study on Lithography Defect Reduction for 19nm NAND SADP Process 5

Study on Lithography Defect Reduction for 19nm NAND SADP Pro...

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5th International Workshop on advanced Patterning Solutions, IWAPS 2021

作者： Ying, Guangchi Dai, Yunqing Wang, Jian Zheng, Hongzhu Shanghai Huali Integrated Circuit Cooperation Advanced Module Techonlogy Development Department Shanghai China

ISBN: (纸本)9781665420785

With the dimension of NAND flash reaching the limit of ArF 193nm immersion scanner by single exposure at half pitch 38nm, the SADP technology (Self Aligned Double Patterning) is utilized to achieve 19nm half pitch CD. However, with the line CD shrinking and cell density increasing, the line broken defects and block etch defects, which are resulting from lithography processing, come to be the key yield killer definitely. In this paper, the defect reduction methodology of HLMC 19nm NAND SADP lithography process, including the line broken defects and block etch defects, is summarized by theoretical analysis and tested by experiment results. The defects are eliminated by RRC pre-clean and enhanced rinse after development, which helps to realize 19NAND mass production and yield improvement, and benefits to more advanced technology nodes development as well. © 2021 IEEE.

关键词： Defects

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An Optimized Method for Cu CMP Dishing Improvement

An Optimized Method for Cu CMP Dishing Improvement

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Zhang, Lei Meng, Yuanyuan Xian, Yi Zhang, Jian Zhou, Haifeng Fang, Jingxun Zhang, Yu Shanghai Huali Integrated Circuit Corporation Advanced Module Technology Development Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

With the development of advanced semiconductor device features shrinking, chemical mechanical polishing (CMP) is becoming an enabling technology to meet the precise machining in various applications. At the same time, the topography of wafer surface shows more and more serious challenges in advanced technology and beyond technology node. Tighten post CMP dishing, pattern loading and uniformity performance control has been evaluated during Cu CMP process. However, it is difficult to improve the Cu dishing and oxide dishing of the interconnect metals for copper CMP process at the same time, because of the selectivity of CMP slurry is fixed. This paper will present how to improve both Cu dishing and oxide dishing control with optimized NDC polish methodology. Experiment results shown that with the NDC CMP process, both Cu and oxide area show better dishing performance. © 2022 IEEE.

关键词： Topography

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Improvement of CU-CMP EDP Curves for Different Pattern Density

Improvement of CU-CMP EDP Curves for Different Pattern Densi...

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Xian, Yi Meng, Yuanyuan Zhang, Lei Zhang, Jian Zhou, Haifeng Fang, Jingxun Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

Transmission rate and pattern density become the key factors affecting CU CMP EDP Curve at advanced node. Different CU line pattern density determines the difference of CMP incoming topography. This incoming pattern loading requires CMP to leave enough Process Window to fix. This article provides the direction of CU CMP EDP optimization for different pattern density products, and focuses on RTPC Remain thickness, so as to improve the CMP process window. © 2022 IEEE.

关键词： Topography

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CMP Scratch Improve in advanced Technology Nodes

CMP Scratch Improve in Advanced Technology Nodes

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Sun, Weiran Yang, Yu Li, Hu Zhao, Wei Xiao, Runcai Zhang, Jian Zhou, Haifeng Fang, Jingxun Zhang, Yu Shanghai Huali Integrated Circuit Corporation Advanced Module Technology Development Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

In the advanced-tech node's shallow trench insulation (STI) chemical mechanical planarization (CMP) process development, by doing design of experiments (DOEs) and repeat runs, the scratch defect count was successfully reduced and kept at 5 count per wafer. In the beginning of development, the process, consumables and tool were used 28nm node's. The scratch defect count in begin was >200eas. The following development improved defect count to 100, 10 at different phases, and finally kept it at 5 count per wafer. The experiment data showed that the updated consumables, improved process parameters, condition type and optimized rinse steps all three factors had significant benefits to scratch defect reduction. © 2022 IEEE.

关键词： Design of experiments

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Pattern Loading Improvement for CU CMP Process

Pattern Loading Improvement for CU CMP Process

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Zhang, Lei Yang, Yu Zhang, Jian Fang, Jingxun Zhang, Yu Shanghai Huali Integrated Circuit Corporation Advanced Module Technology Development Shanghai201314 China

ISBN: (纸本)9798350311006

Chemical mechanical polishing (CMP) is becoming a widely used technology to meet the precise machining in various applications. And also, the topography of pattern wafer surface shows very serious challenges. In semiconductor device, optimize post copper CMP uniformity performance, dishing and pattern loading control have been evaluated during copper CMP process. However, it is difficult to improve the pattern loading of copper and oxide area during copper CMP process, because of the different selectivity of CMP slurry. It is well known that polishing process may cause pattern loading of a layer to be planarization due to uneven distribution of device structures and thus reducing the effectiveness. This paper resent how to improve pattern loading during different pattern density of copper and oxide area, control with optimized barrier slurry and film stack schemes. To achieve the global, as well as local, planarization of wafer surface many innovative technologies have been improvement. A robust copper CMP method with better post CMP profile, tighten metal line sheet resistance (RS), smooth copper surface, and pattern loading control has been evaluated during copper CMP processing. Experiment results shown that there was no pattern loading between dense line area and ISO line area, and better dishing performance with optimized CMP polish methodology. © 2023 IEEE.

关键词： Chemical mechanical polishing

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Study on the Mechanism of CMP Induced W Seam at advanced Technology Node

Study on the Mechanism of CMP Induced W Seam at Advanced Tec...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Zhu, Shaojia Que, Yurong Shi, Feng Yu, Mingfei Zhang, Jian Fang, Jingxun Zhang, Yu Shanghai Huali Integrated Circuit Corporation Advanced Module Technology Development Shanghai201314 China

ISBN: (纸本)9798350311006

W seam is a common defect post WCMP at advanced technology node, which seriously affects the electrical performance of the device and the yield of the chip. The mainly suspected directions are the poor ability of the W gap fill with the CD shrink, or slurry corrosion during the WCMP process. In this paper, we focused the study on influences of WCMP process included oxide loss amount or corrosion caused by slurry soak time increase. First, the different oxide loss amount influence was studied, five wafers with the same incoming condition (gap fill) were processed with the same WCMP recipe body, and given different buffing polish time 20s, 30s, 40s, 50s and 65s for different oxide loss amount. Meanwhile, the five wafer were soaked different time with WCMP slurry. Then the defect was scanned by KLA. The results showed that the number of seam increased significantly when the polish time above 50s. The ILD film thickness of the 5 wafers decreased linearly with the increase of polish time, which proved that seam was buried in the middle of the W plug and gradually exposed on the film surface with the increase of oxide loss amount. By comparison, replace the polish step with slurry soaking step, the seam defect count shows no significant change with the increasing soaking time. The results show that seam is mainly strongly related to the WCMP oxide loss amount instead of WCMP slurry corrosion. © 2023 IEEE.

关键词： Corrosion

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Study on the Correlation Between CMP CU Loading and EDP Curve

Study on the Correlation Between CMP CU Loading and EDP Curv...

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Meng, Yuanyuan Yixian Zhang, Lei Zhang, Jian Zhou, Haifeng Fang, Jingxun Shanghai Huali Integrated Circuit Corporation Advanced Module Technology Development Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

Endpoint detection technology plays an important role in chemical mechanical polishing (CMP) technology, and is affected by many aspects in the actual production process. Because the Endpoint curve can directly reflect the process information, in-depth study of the endpoint curve can predict the health of the process in advance. Taking the AMAT machine as an example, this paper focuses on the influence mechanism of Cu CMP incoming profile such as CU loading on Endpoint, and discusses how to improve endpoint stability to reduce the probability of endpoint capture failure. © 2022 IEEE.

关键词： Chemical mechanical polishing

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An Optimized Monitoring Method for 28HK ILDCMP

An Optimized Monitoring Method for 28HK ILDCMP

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Li, Jingjing Pan, Hongming Yu, Mingfei Zhu, Shaojia Shi, Feng Zhang, Jian Zhou, Haifeng Fang, Jingxun Zhang, Yu Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

In this paper, according to the problems encountered in the research and development of the new generation product of 28HK project of our company, the problems existing in the ILD CMP measurement of the product were improved. The full Map profile and TEM data show that ILDb bond pad cannot reflect the real film thickness of the device area, while OCD pad has a pattern similar to the device area, so the measured value is closer to the actual value. This paper analyzes the reason why OCD pad measurement is closer to the actual value from the perspective of structural difference and CMP dishing. The analysis shows that OCD pad should be selected for subsequent ILD CMP film thickness measurement, and reasonable selection of pad will accelerate the development and mass production efficiency of 28HK products. © 2022 IEEE.

关键词： Production efficiency

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Dishing Improve in advanced Technology Nodes

Dishing Improve in Advanced Technology Nodes

引用

2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Yang, Yu Zhao, Wei Xiao, Runcai Li, Hu Zhang, Jian Zhou, Haifeng Fang, Jingxun Zhang, Yu Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai201314 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

As the semiconductor manufacturing process enters the FinFET node, the process window becomes narrower, and the requirements for the uniformity of chemical mechanical polishing (CMP) become higher, by which the negative effects brought are also unrestricted reduced. As one of the main side effect of CMP, the request of dishing is much stricter in advanced technology. The paper analyzes the causes of dishing, and introduces the control methods of dishing from three aspects: control before dishing generates, optimization during dishing and improvement after dishing exists. Finally, it should be pointed out that the successful stringing of advanced technology requires the coordination and integration of all modules. Only through joint cooperation can the process window be broadened and a win-win situation is achieved. © 2022 IEEE.

关键词： FinFET

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