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7th International Conference on integrated circuits and Microsystems, ICICM 2022

作者： Liu, Haoyan Li, Chun Wang, Wenwu Li, Yongliang University of Chinese Academy of Sciences School of Integrated Circuits Beijing China Institute of Microelectronic Chinese Academy of Sciences Integrated Circuit Advanced Process Center Beijing China

ISBN: (纸本)9781665460439

A novel SiGe fin on insulator (FOI) structure and its FinFET device on a bulk-Si substrate are extensively investigated in this paper. A high-quality SiGe layer epitaxial grown on a Si substrate is realized and a similar notched SiGe/Si fin profile is attained by using the three-step etching process of previous Si FOI structure. However, direct isolation oxidation cannot be applied to get an isolation structure due to lower SiGe thermal stability. Therefore, a SiN film protection post SiGe fin reveal strategy (scheme A) and SiN spacer protection post step-I etching strategy (scheme B) are developed to realize the SiGe FOI structure. Although scheme A can attain a fully oxidation of notched Si fin and no oxidation of SiGe fin, the SiGe fin is distorted due to the large stress induced by the high temperature spike anneal treatment. Compared with the scheme A, a fully isolation of the SiGe fin structure can be achieved and the SiGe fin can maintain well without any oxidation or distorted profile impact. Meanwhile, SiGe FOI FinFET device is also successfully prepared by using the scheme B, which further verifies that it is a practical and effective solution for the fabrication of SiGe FOI structure. © 2022 IEEE.

关键词： Etching

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A Novel FinFET Device with a Four-Period Vertically Stacked SiGe/Si Fin

A Novel FinFET Device with a Four-Period Vertically Stacked ...

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International Conference on integrated circuits and Microsystems (ICICM)

作者： Fei Zhao Yongliang Li Integrated Circuit Advanced Process Center Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665460583

In this work, a novel four-period vertically stacked SiGe/Si FinFET is demonstrated to further boost the electrical performance of the FinFET device. The stacked SiGe/Si fin structure was fabricated successfully by developing the stacked SiGe/Si epitaxial growth and etching processes. Compared with the conventional SiGe channel FinFET, the driven current ION and ION/IOFF ratio of this novel FinFET device increased by 1.6 and ~10 times, respectively. Meanwhile, its subthreshold slope (SS) was improved from 149mV/dec to 90 mV/dec. The improvement of electrical performance can be attributed to the high quality SiGe layer, increased effective channel width, and excellent surface interface properties throughout the whole fabrication process. More importantly, after employing an optimized O 3 passivation technique, its SS and ION/IOFF ratio can be further improved to 75mV/dec and $5\times{10}^{6}$, respectively. The above results strongly suggest that this novel stacked SiGe/Si channel FinFET device is a promising candidate for future technology nodes.

关键词： Performance evaluation Fabrication Micromechanical devices integrated circuits FinFETs Ions Etching

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X-ray irradiation-induced degradation in Hf_(0.5)Zr_(0.5)O_(2) fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

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Rare Metals 2021年第11期40卷 3299-3307页

作者： Yu-Dong Li Qing-Zhu Zhang Fan-Yu Liu Zhao-Hao Zhang Feng-Yuan Zhang Hong-Bin Zhao Bo Li Jiang Yan Key Laboratory of Microelectronics Devices and Integrated Technology Integrated Circuit Advanced Process Center(ICAC)Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100049China State Key Laboratory of Advanced Materials for Smart Sensing GRINM Group Co.LtdBeijing 100088China Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China School of Information Science and Technology North China University of TechnologyBeijing 100144China

The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were *** total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel *** short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold *** was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel ***,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried *** extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was ***,the split capacitance-voltage measurements were used to validate the analysis.

关键词： Total ionizing dose Fully depleted silicon-on-insulator(FDSOI) Metal–oxide–semiconductor field-effect transistor(MOSFET) High-k Hf_(0.5)Zr_(0.5)O_(2)

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Interface Treatment of Epitaxial SI FINFET Channel in Replace Metal Gate with Simultaneously Performance Improvement and Leakage Reduction

Interface Treatment of Epitaxial SI FINFET Channel in Replac...

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China Semiconductor Technology International Conference (CSTIC)

作者： Renjie Jiang Lei Cao Wenjuan Xiong Jiaxin Yao Peng Wang Yadong Zhang Guanqiao Sang Lianlian Li Meihe Zhang Huaxiang Yin Jun Luo Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China State key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

Channel surface defects are an important factor causing poor device interface characteristics and deterioration of sub-threshold characteristics. In order to reduce the interface trap density (Dit) of epitaxial silicon FinFET devices and improve device performance, an in-situ steam generation (ISSG) oxidation and diluted hydrofluoric acid (DHF) cleaning method was proposed to repair the damaged channel surface and reduce the interface defect charge (Q it ) replace metal gate (RMG) module. The thickness of Fin top narrows, and Fin's steepness decreases, after interfacial ISSG oxidation treatment. The electrical results demonstrate that the SS for the NFET with interface treatment are decreased from 74.2 mv/dec to 70.97 mV/dec due to the interface improvement. At the same time, the leakage current reduced from 1.0E-2 μA to 5.67E-4 μA, and the Ion is increased by 16.89% compared with that of conventional FinFET without interface treatment.

关键词： Metals DH-HEMTs Maintenance engineering Logic gates FinFETs Oxidation Silicon

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Investigation of Electrical Characteristics of a Fabricated Lgad Detectors at High and Low Temperatures

Investigation of Electrical Characteristics of a Fabricated ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yupeng Lu Peng Sun Gangping Yan Luoyun Zhang Yanyu Yang Shuang Liu Gaobo Xu Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

The High Granularity Time Detector (HGTD) project need advanced Low-Gain Avalanche Detector (LGAD) for constructing the timing precision layer in the ATLAS detector. It undergoes a strong environmental temperature impact for cooling the absorbed high-energy particles. In this paper, an investigation of the manufacturing process of LGAD detectors and their characteristics in terms of dark current and breakdown voltage at high and low temperatures are systematical explored. The behavior of carrier transport within the device at various temperature conditions was analyzed using TCAD simulation tools.

关键词： integrated circuits Temperature Manufacturing processes Cooling Detectors Dark current Electric variables

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Hybrid simulation method of quantum characteristics for advanced Si MOSFETs under extreme conditions by incorporating simplified master equation with TCAD

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Results in Physics 2024年 63卷

作者： Zhu, Xiaohui Yin, Huaxiang Integrated Circuit Advanced Process R&D Center and State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences University of Chinese Academy of Sciences

Silicon (Si)-based quantum-dot (QD) device by advanced CMOS process is one of important technologies for quantum computing application and currently, it needs a fast and accurate quantum characteristics simulation for designing and optimizing the devices. In this paper, for the first time, a fast hybrid simulation method is proposed by incorporating simplified quantum master equation model with the traditional TCAD tool. Additionally, a SPICE MODEL is incorporated for transient current correction to achieve results closer to real observations. The QD devices forming on advanced stacked Si nanowire (NW) and stacked Si nanosheet (NS) are constructed and simulated by this method, yielding Coulomb diamond plot and charge energies for different structures at 1 K. Notably, a Coulomb blockade region of approximately 82 mV and a first Coulomb step width approximately 1.6 times wider than the blockade region are observed, consistent with theoretical expectations and confirming the method's efficacy. Simulation characteristics of advanced diamond-like channel devices are obtained within 1277 s, demonstrating over 85% matching with experimental data. Meanwhile, the influence of quantum characteristics varying with the transistor's structure and process parameters is also analyzed, which in turn provide a guidance for the design and the optimization of the QD device by advanced Si CMOS process. © 2024

关键词： Hybrid simulation Master equation Quantum dots TCAD

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Stochastic EUV Resist Model

Stochastic EUV Resist Model

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： He, Guangjian Xue, Jing Fan, Taian Wei, Yayi Guangdong Greater Bay Area Institute of Integrated Circuit and System Computational Lithography RD Center Guangzhou China Institute of Microelectronics Chinese Academy of Sciences Achievement Transformation Department Beijing China School of Integrated Circuits Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Advanced Semiconductor Technology Development Department Beijing China

ISBN: (纸本)9798350304510

The stochastic effects in photoresist patterning is of great concern in the implementation of EUV lithography. The stochastic nature of EUV chemically amplified resist requires new modeling approaches rather than the continuous model used in DUV. In this paper, a stochastic model based on Gillespie algorithm is introduced, which subdivides the resist volume into many rectangular small cells and simulates the reaction-diffusion behavior of molecules in a cell volume according to carefully calculated probability. In addition, we further explore the influence of the cell size on the stochastic model. There is an optimal cell size in consideration of precision and running time. When cell size is sufficiently large, the results will approximate to the continuous model. © 2023 IEEE.

关键词： Photoresists

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Improve the Breakdown Voltage of Silicon Pixel Sensor With Optimized Multi-Guard Rings

Improve the Breakdown Voltage of Silicon Pixel Sensor With O...

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China Semiconductor Technology International Conference (CSTIC)

作者： Peng Sun Gaobo Xu Jianyu Fu Mingzheng Ding Yinan Yan Luoyun Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

The silicon pixel sensor (SPS) for X-ray free electron laser detection requires ultra-high operating voltage. In this paper, for an optimized multi-guard rings, a SPS with ultra-high breakdown voltage and low leakage is obtained. The effect of the arrangement of the multi-guard rings on the SPS breakdown is investigated by TCAD simulation. It is found that SPS with a gradually increasing gap from inner ring to outer ring has a higher breakdown voltage. Guided by this, the multi-guard ring structure of SPS is optimized and applied into the manufacture of devices. Finally, the optimized SPS exhibits an ultra-high breakdown voltage of exceeding 1,800 V; and the dark current of per pixel is approximately 2.0 pA at a bias voltage of 1,000 V.

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Improvement of Line Roughness of Fin by Conventional Thermal Oxidation and Atomic Level Low-Temperature Ozone Treatments

Improvement of Line Roughness of Fin by Conventional Thermal...

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China Semiconductor Technology International Conference (CSTIC)

作者： Peng Wang Guanqiao Sang Yihong Lu Wenjuan Xiong Renjie Jiang Lei Cao QingKun Li Lianlian Li Jiaxin Yao Yadong Zhang Meihe Zhang Qingzhu Zhang Junfeng Li Huaxiang Yin Jun Luo Academy of Sciences Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Beijing China University of Chinese Academy of Sciences Beijing China ChangChun University of Science and Technology Changchun China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

In this paper, conventional thermal oxidation (CTO) and atomic level low-temperature ozone (LTO) treatment were utilized to successfully thin the width of fin and reduce the surface roughness. Meanwhile, the line edge roughness (LER) and line width roughness (LWR) of fin were compared under the two schemes. The result show that after three sacrificial oxidizations and DHF rinsing, the LER and LWR of fins were reduced by 40.1% (from 4.64 nm to 2.78 nm) and 55.5% (from 2.38 nm to 1.06 nm), respectively. In addition, after 12 cycles of LTO and HF rinsing, the LER and LWR of fin decreased by 67.4% (from 4.30 nm to 1.40 nm) and 61.3% (from 2.66 nm to 1.03 nm), respectively. And, the cross-correlation coefficients (ρ) were 0.92 and 0.72, respectively. The result provide a guidance for channel surface optimization and low-temperature integration of FinFET devices at advanced technology nodes.

关键词： integrated circuits Gases Hafnium DH-HEMTs FinFETs Oxidation Surface roughness

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Leakage Reduction of GAA Stacked SI Nanosheet CMOS Transistors and 6T-SRAM Cell Via Spacer Bottom Footing Optimization

Leakage Reduction of GAA Stacked SI Nanosheet CMOS Transisto...

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China Semiconductor Technology International Conference (CSTIC)

作者： Jiaxin Yao Xuexiang Zhang Lei Cao Junjie Li Na Zhou Qingkun Li Yanzhao Wei Yanna Luo Jun Luo Qingzhu Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

In this work, the significant leakage reduction approach is proposed and investigated by critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si nanosheet (SiNS) transistors. The fabricated GAA stacked SiNS CMOS transistors and standard 6T static random-access memory (SRAM) cell have achieved reduced static-state leakage current by an order of magnitude and improved read static noise margin (RSNM) by +12.67% due to SBF optimization. The performance boosting origins from improving the gate and source/drain overlap doping profile via SBF optimization, and thus suppressing the band to band tunneling leakage current correspondingly. The proposed leakage reduction approach can inspire and broaden the ultralow power performance application for the state-of-the-art GAA nanosheet technology.

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