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Annual International Symposium on Reliability Physics

作者： E. Sakagami N. Arai H. Tsunoda H. Egawa Y. Yamaguchi E. Kamiya M. Takebuchi K. Yamada K. Yoshikawa S. Mori Semiconductor Device Engineering Laboratory TOSHIBA Corporation Japan Toshiba Microelectronics Corporation Kawasaki Japan Integrated Circuit Advanced Process Department Toshiba Corporation Kawasaki Japan Logic Device Engineering Department Toshiba Corporation Kawasaki Japan

This paper describes the effects of water-related species contained in intermetal dielectric layers on the reliability of nonvolatile memory devices. Charge loss of the cells and hot-carrier (HC) lifetime degradation of peripheral N-channel MOSFETs due to the high temperature bake test are accelerated by the water-related species in the intermetal dielectric layer. The relation between the charge loss and the HC-lifetime degradation and the mechanism involved are discussed. Appropriate dielectric structures to minimize such degradation have been proposed for nonvolatile memory devices with double-metal structure and scaled narrow first metal gaps.< >

关键词： Plasma temperature Nonvolatile memory Degradation circuit testing Dielectric losses Dielectric devices MOSFETs Hot carriers CMOS technology Semiconductor device reliability

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The 2025 2D Materials Roadmap

arXiv

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arXiv 2025年

作者： Ren, Wencai Bøggild, Peter Redwing, Joan Novoselov, Kostya Sun, Luzhao Qi, Yue Jia, Kaicheng Liu, Zhongfan Burton, Oliver Alexander-Webber, Jack Hofmann, Stephan Cao, Yang Long, Yu Yang, Quan-Hong Li, Dan Choi, Soo Ho Kim, Ki Kang Lee, Young Hee Li, Mian Huang, Qing Gogotsi, Yury Clark, Nicholas Carl, Amy Gorbachev, Roman Olsen, Thomas Rosen, Johanna Thygesen, Kristian Sommer Efetov, Dmitri Jessen, Bjarke S. Yankowitz, Matthew Barrier, Julien Kumar, Roshan Krishna Koppens, Frank H.L. Deng, Hui Li, Xiaoqin Dai, Siyuan Basov, D.N. Wang, Xinran Das, Saptarshi Duan, Xiangfeng Yu, Zhihao Borsch, Markus Ferrari, Andrea C. Huber, Rupert Kira, Mackillo Xia, Fengnian Wang, Xiao Wu, Zhong-Shuai Feng, Xinliang Simon, Patrice Cheng, Hui-Ming Liu, Bilu Xie, Yi Jin, Wanqin Nair, Rahul Raveendran Xu, Yan Katiyar, Ajit Ahn, Jong-Hyun Aharonovich, Igor Hersam, Mark C. Roche, Stephan Hua, Qilin Shen, Guozhen Ren, Tianling Zhang, Hao-Bin Koo, Chong Min Koratkar, Nikhil Pellegrini, Vittorio Young, Robert J. Qu, Bill Lemme, Max Pollard, Andrew J. Shenyang National Laboratory for Materials Science Chinese Academy of Sciences China Technical University of Denmark Denmark The Pennsylvania State University United States University of Manchester United Kingdom Institute for Functional Intelligent Materials National University of Singapore Singapore Beijing Graphene Institute China University of Cambridge United Kingdom Department of Chemical Engineering The University of Melbourne Victoria Australia Nanoyang Group Tianjin Key Laboratory of Advanced Carbon and Electrochemical Energy Storage School of Chemical Engineering and Technology Tianjin University Tianjin300072 China The Hong Kong University of Science and Technology Hong Kong Center for Integrated Nanostructure Physics Institute for Basic Science Suwon16419 Korea Republic of Sungkyunkwan University Suwon16419 Korea Republic of Zhejiang Key Laboratory of Data-Driven High-Safety Energy Materials and Applications Ningbo Institute of Materials Technology and Engineering Chinese Academy of Sciences China Drexel University United States Linköping University Sweden Ludwig-Maximilians-Universität München Germany University of Washington United States ICFO The Institute of Photonic Sciences Castelldefels Barcelona08860 Spain University of Michigan United States University of Texas Austin United States Auburn University United States Columbia University United States State Key Laboratory of Catalysis Dalian Institute of Chemical Physics Chinese Academy of Sciences Dalian China University of California Los Angeles United States Suzhou Laboratory Suzhou China School of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing210023 China Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI United States University of Regensburg Germany Department of Electrical and Computer Engineering Yale University New HavenCT United States School of Integrated Circuits Nanjing Uni

Over the past two decades, 2D materials have rapidly evolved into a diverse and expanding family of material platforms. Many members of this materials class have demonstrated their potential to deliver transformative impact on fundamental research and technological applications across different fields. In this roadmap, we provide an overview of the key aspects of 2D material research and development, spanning synthesis, properties and commercial applications. We specifically present roadmaps for high impact 2D materials, including graphene and its derivatives, transition metal dichalcogenides, MXenes as well as their heterostructures and moiré systems. The discussions are organized into thematic sections covering emerging research areas (e.g., twisted electronics, moiré nano-optoelectronics, polaritronics, quantum photonics, and neuromorphic computing), breakthrough applications in key technologies (e.g., 2D transistors, energy storage, electrocatalysis, filtration and separation, thermal management, flexible electronics, sensing, electromagnetic interference shielding, and composites) and other important topics (computational discovery of novel materials, commercialization and standardization). This roadmap focuses on the current research landscape, future challenges and scientific and technological advances required to address, with the intent to provide useful references for promoting the development of 2D materials. © 2025, CC BY.

关键词： Electromagnetic shielding

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Recent progress on submicron electron beam lithography

Recent progress on submicron electron beam lithography

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Electron-Beam, X-Ray, and Ion-Beam Technology for Submicrometer Lithographies V 1986

作者： Takigawa, Tadahiro Shimazaki, Kuniya Kusui, Naoki VLSI Research Center Toshiba R and D Center Toshiba Corporation 1 Komukai Toshibacho Saiwai-ku Kawasaki-city210 Japan Mask Engineering Section Integrated Circuit Advanced Process Engineering Deaprtment Toshiba Corporation 1 Komukai Toshibacho Saiwai-ku Kawasaki-city210 Japan Electron Machine Department Advanced Machine and Equipment Division Toshiba Machine Co. Ltd. 2068-3 Ooka Numazu-city Shizuoka-ken410 Japan

In order to fabricate submicron pattern, total electron beam (EB) lithography system has been developed. Upper submicron pattern will be realized by optical lithography, which requires reticle with high accuracy. An EB writing system, EBM-130/40, has the performance of drawing capability of 4 M bit DRAM reticle pattern in about 40 minutes. The EB system incorporated with peripheral technologies including data compaction conversion software, reticle inspection system, APC-130R, and EBR-9 resist process can produce advanced reticles of number of about 600 per month. For lower submicron pattern formation, next generation lithography system is required. The EBM-130V is the variable shaped EB system with high acceleration voltage of 50 kV and high dosage of 50 μC/cm2 for direct writing and X-ray mask fabrication for development of the high bit density VLSI pattern. This system makes possible EB/optical combined lithography. Its metrology function allows it to measure X-ray mask distortion. © 1986 SPIE. All rights reserved.

关键词： Electron beams

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Vapor phase epitaxy of PbS single-crystal films on water-soluble substrates and application to photodetectors

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Nano Research 2022年第6期15卷 5402-5409页

作者： Yifan Wang Jing Xia Xuanze Li Fan Ru Xue Chen Ze Hua Ruiwen Shao Xuecong Wang Wenjun Zhang Chun-Sing Lee Xiangmin Meng Key Laboratory of Photochemical Conversion and Optoelectronic Materials Technical Institute of Physics and ChemistryChinese Academy of SciencesBeijing 100190China Institute of Process Engineering Chinese Academy of SciencesBeijing 100190China Centre of Material Science and Optoelectronic Engineering University of Chinese Academy of SciencesBeijing 10049China Engineering Research Center for Semiconductor Integrated Technology Institute of SemiconductorsChinese Academy of SciencesBeijing 100083China Analysis&Testing Center Beijing Institute of TechnologyBeijing 102488China Beijing Advanced Innovation Center for Intelligent Robots and Systems and Institute of Convergence in Medicine and Engineering Beijing Institute of TechnologyBeijing 100081China Center of Super-Diamond and Advanced Films(COSADF)and Department of Materials Science and Engineering City University of Hong KongHong KongChina Center of Super-Diamond and Advanced Films(COSDAF)and Department of Chemistry City University of Hong KongHong KongChina

Lead sulfide(PbS),a typical functional semiconductor material,has attracted serious attention due to its great potential in optoelectronics ***,controllable growth of PbS single-crystal film still remains a great ***,we report heteroepitaxial growth of large-scale highly crystalline PbS films on alkali salt(NaCl and KCl)substrates via chemical vapor deposition(CVD).Structural characterizations demonstrate that the as-grown PbS films exhibit an atomically sharp interface with the underlying *** epitaxial relationships between the epilayers and substrates were determined to be PbS(100)//NaCl(100)or KCl(100),PbS[010]//NaCl[010]or KCl[010].Owing to the high solubility of alkali salt,the epitaxial PbS films can be rapidly released from the underlying substrates and transferred to other substrates of interest while maintaining good integrity and crystallinity,the process of which is particularly attractive in the fields of electronics and ***,photodetectors based on the transferred PbS films were fabricated,exhibiting a high photoresponsivity of 7.5 A/W,a detectivity of 1.44×10^(12)Jones,and a rapid response time of approximately 0.25 *** work sheds light on the batch production,green transfer,and optoelectronic application of PbS films.

关键词： heteroepitaxial growth lead sulfide(PbS) single-crystal film photodetector transferable

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Manipulating the topological phase of coupled modes in a plasmonic array via engineering near-field asymmetry: From zigzag arrangement to dielectric substrate

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Physical Review B 2024年第8期110卷 085407-085407页

作者： Huizhou Wu Z. Z. Liu G. C. Wei Q. Zhang Jun-Jun Xiao College of Electronic and Information Engineering and Shenzhen Engineering Laboratory of Aerospace Detection and Imaging Research Center for Advanced Optics and Photoelectronics Department of Physics College of Science School of Mathematical and Physical Sciences Department of Physics and Optoelectronics College of Integrated Circuit

Photonic nanoparticle arrays that exhibit topologically nontrivial phases are often established by arranging nanoparticles in a lattice configuration in analog to the Su-Schrieffer-Heeger model. This design strategy is based on the principle that the optical interactions among the nanoparticles are predominantly dictated by the distances between them. However, these interactions are also significantly shaped by the near-field profiles of the nanoparticles. As an exemplary case, we examine a zigzag array of metallic ellipsoidal nanoparticles (ENPs) and illustrate how the topological phase of coupled plasmonic waves in such an array can be manipulated by controlling the orientation of the ENPs. More intriguingly, the near-field characteristics of the ENPs can be fine-tuned by the presence of a substrate, suggesting an alternative avenue for modulating the inter-particle interactions. We further show that topological phase transitions in both one-dimensional (1D) and 2D ENP arrays can be triggered by introducing a nearby dielectric substrate, while maintaining the original lattice structure unchanged. Our findings reveal a different mechanism for modulating the topological phases of nanoparticle arrays and provide a strategy that could be extrapolated to other photonic and classical wave systems, suggesting possibilities for the design and control of topological states in carefully engineered photonic systems.

关键词： Plasmonics Topological effects in photonic systems Nanoparticles Discrete dipole approximation

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PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog circuit Synthesis 24

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Fram...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Kong, Zichen Tang, Xiyuan Shi, Wei Du, Yiheng Lin, Yibo Wang, Yuan School of Integrated Circuits Peking University China Institute for Artificial Intelligence Peking University China Mpw Center Peking University China Department of Electrical and Computer Engineering The University of Texas Austin United States Yuanpei College Peking University China Beijing Laboratory of Future Integrated Circuit Technology and Science Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400706011

With the CMOS technology advancing and the complexity of circuits growing, the demand for analog/mixed-signal design automation tools is increasing quickly. Although some tools have been developed to tackle this challenge, the performance degradation caused by process, voltage, and temperature (PVT) variations has been less considered. This paper presents PVTSizing, an optimization framework for PVT-robust analog circuit synthesis. PVTSizing adopts trust region Bayesian optimization (TuRBO) for high-quality initial datasets and reference points. Multi-task reinforcement learning (RL) is utilized for PVT optimization. Both TuRBO and RL are batch-friendly, allowing parallel sampling of design solutions. Meanwhile, critic-assisted pruning and zoom target metrics are proposed to improve sample efficiency and reduce runtime. In addition, this framework naturally supports sizing over random mismatch. On 4 real-world circuits with TSMC 28/180nm process, PVTSizing achieves 1.9× - 8.8× sample efficiency and 1.6× - 9.8× time efficiency improvements compared to prior sizing tools from both industry and academia. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Reinforcement learning

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Photon emission study of ESD protection devices under second breakdown conditions

Photon emission study of ESD protection devices under second...

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Annual International Symposium on Reliability Physics

作者： H. Ishizuka K. Okuyama K. Kubota Hitachi Yonezawa Electronics Company Limited Yamagata Japan Process Engineering Development Department Semiconductor and Integrated Circuit Div Hitachi and Limited Tokyo Japan

The relationship between ESD performance and photon emission from MOSFETs under breakdown conditions has been studied for various drain structures. Since ESD protection level is well correlated with current driveability in the second breakdown region, observation of the spatial distribution of photon emission provides new insight to the understanding of breakdown behaviors resulting in different ESD performance. The photon emission study revealed that the three-dimensional progression of breakdown behaviors depends on drain structures and are correlated with ESD performance.< >

关键词： Electrostatic discharge Protection Electric breakdown Photonic integrated circuits MOSFETs Hot carriers Degradation Breakdown voltage Semiconductor device breakdown Optical filters

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process and device technologies for 16 Mbit EPROMs with large-tilt-angle implanted p-pocket cell

Process and device technologies for 16 Mbit EPROMs with larg...

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International Electron Devices Meeting (IEDM)

作者： Y. Ohshima S. Mori Y. Kaneko E. Sakagami N. Arai N. Hosokawa K. Yoshikawa Semiconductor Device Engineering Laboratories Toshiba Corporation Kawasaki Japan Toshiba Microelectronics Corporation Kawasaki Japan Integrated Circuit Process Engineering Department Toshiba Corporation Kawasaki Japan

A reliable high-performance process and device technologies for the fabrication of a 0.6 mu m 16 Mbit CMOS EPROM have been developed. A novel cell structure called a LAP cell is proposed, which yields stable high performance in the 0.6 mu m regime. The important processes and device technologies are a large-tilt-angle implanted p-pocket (LAP) cell structure with 0.6 mu m gate length, a self-aligned source (SAS) technology, a poly-Si plugged-contact technology for CMOS devices via a novel multistep poly-Si deposition method, and a 0.8 mu m poly-Si shield isolation structure for high voltage circuits. It is noted that these technologies together with advanced lithography techniques will be sufficient for the manufacture of future 64 Mbit EPROMs and beyond.< >

关键词： EPROM CMOS technology Isolation technology CMOS process Fabrication Synthetic aperture sonar Voltage circuits Lithography Manufacturing

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Stochastic EUV Resist Model

Stochastic EUV Resist Model

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： He, Guangjian Xue, Jing Fan, Taian Wei, Yayi Guangdong Greater Bay Area Institute of Integrated Circuit and System Computational Lithography RD Center Guangzhou China Institute of Microelectronics Chinese Academy of Sciences Achievement Transformation Department Beijing China School of Integrated Circuits Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Advanced Semiconductor Technology Development Department Beijing China

ISBN: (纸本)9798350304510

The stochastic effects in photoresist patterning is of great concern in the implementation of EUV lithography. The stochastic nature of EUV chemically amplified resist requires new modeling approaches rather than the continuous model used in DUV. In this paper, a stochastic model based on Gillespie algorithm is introduced, which subdivides the resist volume into many rectangular small cells and simulates the reaction-diffusion behavior of molecules in a cell volume according to carefully calculated probability. In addition, we further explore the influence of the cell size on the stochastic model. There is an optimal cell size in consideration of precision and running time. When cell size is sufficiently large, the results will approximate to the continuous model. © 2023 IEEE.

关键词： Photoresists

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A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

A stacked split word-line (SSW) cell for low-voltage operati...

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International Electron Devices Meeting (IEDM)

作者： S. Ikeda K. Asayama N. Hashimoto E. Fujita Y. Yoshida A. Koike T. Yamanaka K. Ishibashi S. Meguro Process Engineering Development Department Semiconductor and Integrated Circuit Division Hitachi and Limited Tokyo Japan Hitachi VLSI Engineering Corporation Limited Central Research Laboratory Hitachi and Limited Japan

Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.< >

关键词： Random access memory Etching Thin film transistors Oxidation Plasma applications Silicon Capacitors Rough surfaces Surface roughness Plasma measurements

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