检索结果-内蒙古大学图书馆

China Semiconductor Technology International Conference (CSTIC)

作者： Peng Wang Guanqiao Sang Yihong Lu Wenjuan Xiong renjie Jiang Lei Cao QingKun Li Lianlian Li Jiaxin Yao Yadong Zhang Meihe Zhang Qingzhu Zhang Junfeng Li Huaxiang Yin Jun Luo Academy of Sciences Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Beijing China University of Chinese Academy of Sciences Beijing China ChangChun University of Science and Technology Changchun China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

In this paper, conventional thermal oxidation (CTO) and atomic level low-temperature ozone (LTO) treatment were utilized to successfully thin the width of fin and reduce the surface roughness. Meanwhile, the line edge roughness (LEr) and line width roughness (LWr) of fin were compared under the two schemes. The result show that after three sacrificial oxidizations and dHF rinsing, the LEr and LWr of fins were reduced by 40.1% (from 4.64 nm to 2.78 nm) and 55.5% (from 2.38 nm to 1.06 nm), respectively. In addition, after 12 cycles of LTO and HF rinsing, the LEr and LWr of fin decreased by 67.4% (from 4.30 nm to 1.40 nm) and 61.3% (from 2.66 nm to 1.03 nm), respectively. And, the cross-correlation coefficients (ρ) were 0.92 and 0.72, respectively. The result provide a guidance for channel surface optimization and low-temperature integration of FinFET devices at advanced technology nodes.

关键词： integrated circuits Gases Hafnium dH-HEMTs FinFETs Oxidation Surface roughness

来源：评论

学校读者我要写书评

暂无评论

Fast Simulation of Quantum Characteristics for advanced Si Mosfets Under Extreme Conditions by Incorporating Simplified Master Equation with Tcad

SSRN

引用

SSrN 2023年

作者： Zhu, Xiaohui Yin, Huaxiang The Integrated Circuit Advanced Process R&D Center State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing100029 China The School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China

Silicon (Si)-based quantum-dot (Qd) device by advanced CMOS process is one of important technologies for quantum computing application and currently . In this paper, for the first time, a fast hybrid simulation method is proposed by incorporating simplified quantum master equation model with the traditional TCAd tool. The Qd devices forming on advanced stacked Si nanowire (NW) and stacked Si nanosheet (NS) are constructed, extracted and simulated by the method. The diamond-like charge stability diagram and the different charge energy between structures are accurately simulated at efficient time cost. With the new introduced transient current correction by SPICE model, the simulated results show great matching degree with those actual characteristics of advanced diamond-like device under 4 K. Meanwhile, the influence of quantum characteristics varying with the transistor ’ s structure and process parameters is also analyzed, which in turn provide a guidance for the design and the optimization of the Qd device by advanced Si CMOS process. © 2023, The Authors. All rights reserved.

关键词： Silicon

来源：评论

学校读者我要写书评

暂无评论

Hybrid Simulation Method of Quantum Characteristics for advanced Si Mosfets Under Extreme Conditions by Incorporating Simplified Master Equation with Tcad

SSRN

引用

SSrN 2024年

作者： Zhu, Xiaohui Yin, Huaxiang Integrated Circuit Advanced Process R&D Center State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics The Chinese Academy of Sciences Beijing Beijing100029 China University of Chinese Academy of Sciences Beijing Beijing100049 China

Silicon (Si)-based quantum-dot (Qd) device by advanced CMOS process is one of important technologies for quantum computing application and currently, it needs a fast and accurate quantum characteristics simulation for designing and optimizing the devices. In this paper, for the first time, a fast hybrid simulation method is proposed by incorporating simplified quantum master equation model with the traditional TCAd tool. Additionally, a SPICE MOdEL is incorporated for transient current correction to achieve results closer to real observations. The Qd devices forming on advanced stacked Si nanowire (NW) and stacked Si nanosheet (NS) are constructed and simulated by this method, yielding Coulomb diamond plot and charge energies for different structures at 1K. Notably, a Coulomb blockade region of approximately 82mV and a first Coulomb step width approximately 1.6 times wider than the blockade region are observed, consistent with theoretical expectations and confirming the method's efficacy. Simulation characteristics of advanced diamond-like channel devices are obtained within 1277 seconds, demonstrating over 85% matching with experimental data. Meanwhile, the influence of quantum characteristics varying with the transistor’s structure and process parameters is also analyzed, which in turn provide a guidance for the design and the optimization of the Qd device by advanced Si CMOS process. © 2024, The Authors. All rights reserved.

关键词： Silicon

来源：评论

学校读者我要写书评

暂无评论

Leakage reduction of GAA Stacked SI Nanosheet CMOS Transistors and 6T-SrAM Cell Via Spacer Bottom Footing Optimization

Leakage Reduction of GAA Stacked SI Nanosheet CMOS Transisto...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Jiaxin Yao Xuexiang Zhang Lei Cao Junjie Li Na Zhou Qingkun Li Yanzhao Wei Yanna Luo Jun Luo Qingzhu Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

In this work, the significant leakage reduction approach is proposed and investigated by critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si nanosheet (SiNS) transistors. The fabricated GAA stacked SiNS CMOS transistors and standard 6T static random-access memory (SrAM) cell have achieved reduced static-state leakage current by an order of magnitude and improved read static noise margin (rSNM) by +12.67% due to SBF optimization. The performance boosting origins from improving the gate and source/drain overlap doping profile via SBF optimization, and thus suppressing the band to band tunneling leakage current correspondingly. The proposed leakage reduction approach can inspire and broaden the ultralow power performance application for the state-of-the-art GAA nanosheet technology.

关键词：

来源：评论

学校读者我要写书评

暂无评论

record 7(N)+7(P) Multiple VTs demonstration on GAA Si Nanosheet n/pFETs using WFM-Less direct Interfacial La/Al-dipole Technique

Record 7(N)+7(P) Multiple VTs Demonstration on GAA Si Nanosh...

引用

International Electron devices Meeting (IEdM)

作者： Jiaxin Yao Yanzhao Wei Shuai Yang Hong Yang Gaobo Xu Yadong Zhang Lei Cao Xuexiang Zhang Qianqian Liu Zhenhua Wu Huaxiang Yin Qingzhu Zhang Junfeng Li Jun Luo Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665489607

In this paper, for the first time, we have realized record 7(N)+7(P) multiple threshold voltages (Multi-V T s) on horizontal gate-all-around (GAA) Si nanosheet (SiNS) n/pFETs using work-function-metal-less (WFM-less) direct interfacial La/Al-dipole technique, regardless of the sheet-to-sheet spacing (T sus ) pinch-off in stacked channels. Owning to higher dipole intensity in ultra-thin high-k dielectric (HK) films obtained by ALd in-situ direct dual dielectric La-/Al-dipole (d 4 ) control between adjacent NSs, both nFETs and pFETs have achieved 7 V T s (1 rVT, 3 HVT and 3 LVT) with good uniformity and discrimination even in WFM-less gate stack. The maximum V T tuning ranges reach 1105 mV/873 mV and the minimum discriminable ΔV T over 83mV/76mV for n/pFETs, respectively, exhibiting great multi-V T s application advantages for future high performance and low power GAA SiNS CMOS process.

关键词： Performance evaluation degradation Gallium arsenide Logic gates Electron mobility Silicon Hafnium compounds

来源：评论

学校读者我要写书评

暂无评论

Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2 Bi-Layer dipole-First process Using PVd Method for advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Yanzhao Wei Jiaxin Yao renren Xu Qingzhu Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

In this paper, a La 2 O 3 /HfO 2 bi-layer dipole-first (dF) process is proposed and investigated by ultra-low temperature PVd dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3d-IC (M3d) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (V FB ) negatively shifts 60 mV with sub-1nm La 2 O 3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (dit) are suppressed by La 2 O 3 /HfO 2 bi-layer dF process to improve device performance. These results exhibit a promising bi-layer dF process in low thermal integration for advanced IC technology.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Interface Treatment of Epitaxial SI FINFET Channel in replace Metal Gate with Simultaneously Performance Improvement and Leakage reduction

Interface Treatment of Epitaxial SI FINFET Channel in Replac...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： renjie Jiang Lei Cao Wenjuan Xiong Jiaxin Yao Peng Wang Yadong Zhang Guanqiao Sang Lianlian Li Meihe Zhang Huaxiang Yin Jun Luo Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China State key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

Channel surface defects are an important factor causing poor device interface characteristics and deterioration of sub-threshold characteristics. In order to reduce the interface trap density (dit) of epitaxial silicon FinFET devices and improve device performance, an in-situ steam generation (ISSG) oxidation and diluted hydrofluoric acid (dHF) cleaning method was proposed to repair the damaged channel surface and reduce the interface defect charge (Q it ) replace metal gate (rMG) module. The thickness of Fin top narrows, and Fin's steepness decreases, after interfacial ISSG oxidation treatment. The electrical results demonstrate that the SS for the NFET with interface treatment are decreased from 74.2 mv/dec to 70.97 mV/dec due to the interface improvement. At the same time, the leakage current reduced from 1.0E-2 μA to 5.67E-4 μA, and the Ion is increased by 16.89% compared with that of conventional FinFET without interface treatment.

关键词： Metals dH-HEMTs Maintenance engineering Logic gates FinFETs Oxidation Silicon

来源：评论

学校读者我要写书评

暂无评论

Investigation of Electrical Characteristics of a Fabricated Lgad detectors at High and Low Temperatures

Investigation of Electrical Characteristics of a Fabricated ...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Yupeng Lu Peng Sun Gangping Yan Luoyun Zhang Yanyu Yang Shuang Liu Gaobo Xu Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

The High Granularity Time detector (HGTd) project need advanced Low-Gain Avalanche detector (LGAd) for constructing the timing precision layer in the ATLAS detector. It undergoes a strong environmental temperature impact for cooling the absorbed high-energy particles. In this paper, an investigation of the manufacturing process of LGAd detectors and their characteristics in terms of dark current and breakdown voltage at high and low temperatures are systematical explored. The behavior of carrier transport within the device at various temperature conditions was analyzed using TCAd simulation tools.

关键词： integrated circuits Temperature Manufacturing processes Cooling detectors dark current Electric variables

来源：评论

学校读者我要写书评

暂无评论

recent progress on submicron electron beam lithography

Recent progress on submicron electron beam lithography

引用

Electron-Beam, X-ray, and Ion-Beam Technology for Submicrometer Lithographies V 1986

作者： Takigawa, Tadahiro Shimazaki, Kuniya Kusui, Naoki VLSI Research Center Toshiba R and D Center Toshiba Corporation 1 Komukai Toshibacho Saiwai-ku Kawasaki-city210 Japan Mask Engineering Section Integrated Circuit Advanced Process Engineering Deaprtment Toshiba Corporation 1 Komukai Toshibacho Saiwai-ku Kawasaki-city210 Japan Electron Machine Department Advanced Machine and Equipment Division Toshiba Machine Co. Ltd. 2068-3 Ooka Numazu-city Shizuoka-ken410 Japan

In order to fabricate submicron pattern, total electron beam (EB) lithography system has been developed. Upper submicron pattern will be realized by optical lithography, which requires reticle with high accuracy. An EB writing system, EBM-130/40, has the performance of drawing capability of 4 M bit drAM reticle pattern in about 40 minutes. The EB system incorporated with peripheral technologies including data compaction conversion software, reticle inspection system, APC-130r, and EBr-9 resist process can produce advanced reticles of number of about 600 per month. For lower submicron pattern formation, next generation lithography system is required. The EBM-130V is the variable shaped EB system with high acceleration voltage of 50 kV and high dosage of 50 μC/cm2 for direct writing and X-ray mask fabrication for development of the high bit density VLSI pattern. This system makes possible EB/optical combined lithography. Its metrology function allows it to measure X-ray mask distortion. © 1986 SPIE. All rights reserved.

关键词： Electron beams

来源：评论

学校读者我要写书评

暂无评论

Impact of Thickness dependent Ferroelectric and Interface Charge Variation on device-to-device Variation in Ferroelectric FET

Impact of Thickness Dependent Ferroelectric and Interface Ch...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Fan Zhang Zhaohao Zhang Jiali Huo Qingzhu Zhang Gaobo Xu Zhenhua Wu Genquan Han Huaxiang Yin Yan Liu State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology School of Microelectronics Xidian University Xi'an China Integrated Circuit Advanced Process R&D Center and the State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

In this work, the film thickness-dependent threshold voltage $(V_{\text{TH}})$ variation is investigated theoretically through statistical Monte Carlo simulation. An improved VTH variation is found in the 6 nm $\text{Hf}_{0.5}\text{Zr}_{0.5}\mathrm{O}_r$ (HZO) gate insulator under the coupling effect of ferroelectric parameters and interface charge density fluctuations, in comparison to thicker HZO films. The increase in trap density significantly deteriorates the $V_{\text{TH}}$ variation, which can be mitigated by the enlarged charge response in the thin film. This work provides a guideline for variation performance improvement in building reliable ultra-scale integrated circuits.

关键词： integrated circuits Performance evaluation Couplings Monte Carlo methods Fluctuations Buildings Iron

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：