In this paper, a new ultra-thin fully-depleted SOI CMOS structure with sharing contact between source/drain and back gate is presented to save area and increase threshold voltage tuning capability. TCAd simulations ar...
In this paper, a new ultra-thin fully-depleted SOI CMOS structure with sharing contact between source/drain and back gate is presented to save area and increase threshold voltage tuning capability. TCAd simulations are used to investigate the back-gate effect on the ultra-thin SOI CMOS. A new process flow to make the fully-depleted SOI CMOS structures is also proposed.
作者：
Hayashi, TFukuda, KOhno, MNishi, KKita, AVLSI R&D Center
OKI Electric Industry Company Ltd. Hachioji-shi Japan 193 Graduated from the Science University of Tokyo
Dept. of Applied Physics in 1986 and joined Oki Electric. Since then he has been engaged in research on the reliability of MOS transistors and silicon oxide films. Since 1994 he has been engaged in the development of flash memory. He is a member of the Applied Physics Society. Graduated from the University of Tokyo
Dept. of Applied Physics in 1983 and joined Oki Electric in 1985. Since then he has been engaged in research on the semiconductor process and device simulation. In 1990 he participated in joint research at the Technical University of Aachen. He is a member of the Applied Physics Society. Graduated from the Tokyo University of Agriculture and Technology
Dept. of Electrical Engineering in 1980 and completed an MS course in 1983. In 1986 he completed the doctoral course at Shizuoka University. He then joined Oki Electric where he has been engaged in research on ULSI processes. He is now a manager responsible for flash memory at the VLSI R&D Center. He holds a doctorate in engineering. He is a member of the Applied Physics Society. Graduated from the University of Tokyo
Dept. of Applied Physics in 1973 and joined Oki Electric. He was engaged in the development of integrated circuit logic simulation technology and bipolar process technology and since 1980 he has been engaged in research on process/device simulation and modeling. Presently he is a senior manager at the VLSI R&D Center. In 1982–1984 he was a Visiting Scholar at MIT. He holds a doctorate in engineering. He is a member of the Applied Physics Society and a senior member of IEEE. Graduated from Tokyo Institute of Technology
Dept. of Chemical Engineering in 1978 and completed the MS program in 1930. In that year he joined Oki Electric. Since then he has been engaged in CMOS process design for DRAM and flash memory. He is now a manager at the VLSI R&D Center. He is a member of the Applied Physics Society.
In order to analyze the BBT (band-to-band tunneling) phenomenon in flash memory cells by simulation, a new model is proposed, which improves on the BBT model by introducing the concept of ''average electric fi...
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In order to analyze the BBT (band-to-band tunneling) phenomenon in flash memory cells by simulation, a new model is proposed, which improves on the BBT model by introducing the concept of ''average electric field.'' This model agrees well with the measuredresults in a wide drain N-concentration range. Using this model, the reliability of memory cells is analyzed. It is found that the difference of the amount of BBT generation does not directly affect the endurance characteristics but does affect the disturb characteristics. The same model can be used to analyze problem points of the present cells and to estimate the BBT current of next-generation devices accurately.
With one- and two-qubit gate fidelities approaching the fault-tolerance threshold for spin qubits in Si, how to scale up the architecture and make large arrays of spin qubits become the more pressing challenges. In a ...
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A scanner matching method based on interior-point BFGS algorithm is proposed. This method minimizes the critical dimension (Cd) differences by optimizing parameters of illumination sources, including inner partial coh...
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ISBN:
(纸本)9781665420808
A scanner matching method based on interior-point BFGS algorithm is proposed. This method minimizes the critical dimension (Cd) differences by optimizing parameters of illumination sources, including inner partial coherence factor, outer partial coherence factor, numerical aperture and opening angle of illumination poles fordipole and quadrupole sources. Simulations of scanner matching are performed. Scanners with annular, dipole and quadrupole sources are matched in the simulations. Through-pitch Line/space patterns are used as the matching targets. The results of these simulations show that, the proposed method can reduce root-mean-square of Cddifferences after matching. In the majority of the simulation cases, the proposed method is faster than methods based on the Levenberg-Marquardt algorithm, and could even achieve betterresult. Analyses on the proposed method are given.
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