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Correcting on-chip distortion of control pulses with silicon spin qubits

Chinese Physics B 2025年第1期34卷 265-271页

作者： Ming Ni Rong-Long Ma Zhen-Zhen Kong Ning Chu Wei-Zhu Liao Sheng-Kai Zhu Chu Wang Gang Luo Di Liu Gang Cao Gui-Lei Wang Hai-Ou Li Guo-Ping Guo CAS Key Laboratory of Quantum Information University of Science and Technology of China(USTC)Hefei 230026China CAS Center for Excellence in Quantum Information and Quantum Physics University of Science and Technology of ChinaHefei 230026China Integrated Circuit Advanced Process Research and Development Center Institute of MicroelectronicsChinese Academy of Sciences(CAS)Beijing 100029China Hefei National Laboratory Hefei 230088China Beijing Superstring Academy of Memory Technology Beijing 100176China Origin Quantum Computing Company Limited Hefei 230026China

In semiconductor quantum dot systems,pulse distortion is a significant source of coherent errors,which impedes qubit characterization and ***,we demonstrate two calibration methods using a two-qubit system as the detector to correct distortion and calibrate the transfer function of the control *** methods are straightforward to implement,robust against noise,and applicable to a wide range of qubit *** two methods differ in correction accuracy and *** first,coarse predistortion(CPD)method,partially mitigates *** second,all predistortion(APD)method,measures the transfer function and significantly enhances exchange oscillation *** methods use exchange oscillation homogeneity as the metric and are suitable for any qubit driven by a diabatic *** believe these methods will enhance qubit characterization accuracy and operation quality in future applications.

关键词： quantum computation quantum dot pulse distortion

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Supercritical carbon dioxide process for releasing stuck cantilever beams

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Journal of Semiconductors 2010年第10期31卷 126-129页

作者：惠瑜高超群王磊景玉鹏 Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of Sciences

The multi-SCCO2 （supercritical carbon dioxide） release and dry process based on our specialized SCCO2 semiconductor process equipment is investigated and the releasing mechanism is discussed. The experiment results show that stuck cantilever beams were held up again under SCCO2 high pressure treatment and the repeatability of this process is nearly 100%.

关键词： SCCO2 sticking effect release cantilever beam MEMS

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Diverse set of two-qubit gates for spin qubits in semiconductor quantum dots

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Physical Review Applied 2025年第2期23卷 024065-024065页

作者： Ming Ni Rong-Long Ma Zhen-Zhen Kong Ning Chu Sheng-Kai Zhu Chu Wang Ao-Ran Li Wei-Zhu Liao Gang Cao CAS Key Laboratory of Quantum Information University of Science and Technology of China Hefei Anhui 230026 China CAS Center for Excellence in Quantum Information and Quantum Physics University of Science and Technology of China Hefei Anhui 230026 China Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 P. R. China Hefei National Laboratory University of Science and Technology of China Hefei 230088 China

On the path toward large-scale quantum information processing, the ability to implement diverse types of two-qubit gates is preferable for device structure designs and quantum circuit compilations. Here, taking advantage of the inherent Heisenberg interaction between spin qubits, we propose and verify a fast composite two-qubit gate scheme for spin qubits based on semiconductor quantum dots. Theoretical results indicate that the gate scheme facilitates the simultaneous implementation of various types of two-qubit gates, including five types of essential two-qubit gates, iswap-family gates, and fermionic simulation gates. Furthermore, we observe an excellent match between the measured and simulated results, representing the preliminary experimental demonstration of the composite gate scheme. We believe that, with this versatile composite two-qubit gate scheme, the available broad-spectrum two-qubit operations will allow us to efficiently utilize the hardware resources and accelerate the advancement of noisy intermediate-scale quantum computing.

关键词： Semiconductor quantum dots

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Key technologies for dual high-k and dual metal gate integration

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Chinese Physics B 2018年第9期27卷 529-534页

作者： Yong-Liang Li Qiu-Xia Xu@ and Wen-Wu Wang Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of ScienceBeijing 100029China

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and *** that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

关键词： high-k metal gate metal insert poly-Si stack(MIPS) dual high-k and dual metal gate(DHDMG)

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High crystalline quality of SiGe fin fabrication with Si-rich composition area using replacement fin processing

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Chinese Physics B 2020年第8期29卷 441-444页

作者： Ying Zan Yong-Liang Li Xiao-Hong Cheng Zhi-Qian Zhao Hao-Yan Liu Zhen-Hua Hu An-Yan Du Wen-Wu Wang Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China

A high crystalline quality of SiGe fin with an Si-rich composition area using the replacement fin processing is systematically demonstrated in this *** fin replacement process based on a standard FinFET process is developed.A width of less than 20-nm SiGe fin without obvious defect impact both in the direction across the fin and in the direction along the fin is verified by using the high angle annular dark field scanning transmission electron microscopy and the scanning moiréfringe imaging ***,the SiGe composition is inhomogenous in the width of the *** is induced by the formation of 111 *** to the atomic density of the 111 facets being higher,the epitaxial growth in the direction perpendicular to these facets is slower than in the direction perpendicular to *** Ge incorporation is then higher on the 111 facets than on the 001 ***,an Si-rich area is observed in the central area and on the bottom of SiGe fin.

关键词： SiGe selective epitaxial growth FinFET replacement fin processing

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Study on electrothermally actuated cantilever array for nanolithography

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Science China(Technological Sciences) 2010年第5期53卷 1184-1189页

作者： FU JianYu,CHEN DaPeng & YE TianChun integrated circuit advanced process center,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China 1. Integrated Circuit Advanced Process Center Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China

Nanolithography is a patterning technique for the fabrication of nano-scale structures.A promising method of nanolithography known as scanning probe lithography has particularly extensive applications for its high resolution,high reliability,and simple *** this paper,a novel electrothermally actuated cantilever with integrated heater,thermal conductor and actuator for scanning probe lithography is *** are designed in an 8×4 *** models are presented to simulate the temperature distribution,deflection and thermal crosstalk of the cantilever *** structure is successfully *** is demonstrated that this structure can produce a tip deflection of 16.9 μm at an actuation current of 5.5 mA and the thermal crosstalk between the cantilevers is neglected.

关键词： nanolithography scanning probe lithography electrothermal actuation

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High-Mobility P-Type MOSFETs with integrated Strained-Si_(0.73)Ge_(0.27) Channels and High-κ/Metal Gates

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Chinese Physics Letters 2016年第11期33卷 127-130页

作者：毛淑娟朱正勇王桂磊朱慧珑李俊峰赵超 Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of Sciences Key Laboratory of Microelectronics Devices & Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences

Strained-Si0.73Ge0.27 channels are successfully integrated with high-R/metal gates in p-type metai-oxide- semi- conductor field effect transistors （pMOSFETs） using the replacement post-gate process. A silicon cap and oxide inter layers are inserted between Si0.73Ge0.27 and high-κ dielectric to improve the interface. The fab- ricated Si0.73Ge0.27 pMOSFETs with gate length of 3Onto exhibit good performance with high drive current （~428μA/μm at VDD = 1 V） and suppressed short-channel effects （DIBL^77mV/V and SS^90mV/decade）. It is found that the enhancement of effective hole mobility is up to 200% in long-gate-length Si0.73Ge0.27-channel pMOSFETs compared with the corresponding silicon transistors. The improvement of device performance is reduced due to strain relaxation as the gate length decreases, while 26% increase of the drive current is still obtained for 30-nm-gate-length Si0.73Ge0.27 devices.

关键词： with is Channels and High Metal Gates High-Mobility P-Type MOSFETs with integrated Strained-Si Ge of in

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Narrowed Si_(0.7)Ge_(0.3)channel FinFET with subthreshold swing of64 mV/Dec using cyclic self-limited oxidation and removal process

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Chinese Physics B 2023年第7期32卷 500-503页

作者：刘昊炎李永亮王文武 Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of ScienceBeijing 100029China University of Chinese Academy of Sciences(UCAS) Beijing 100049China

A narrowed Si_(0.7)Ge_(0.3)channel fin field-effect transistor(FinFET)device is demonstrated in detail by using an accuratecyclic wet treatment *** Si_(0.7)Ge_(0.3)fin/per side of 0.63 nm in thickness can be accurately removed in each cycleby utilizing a self-limited oxidation with 40%HNO_(3)solution in 40 s and oxidation removal can be achieved with 1%HFsolution in 10 *** a result,after the dummy gate removal,the fin width of Si_(0.7)Ge_(0.3)can be narrowed from 20 nm to 8 nmby utilizing 10 cycles of this wet treatment *** with the conventional Si_(0.7)Ge_(0.3)FinFET under a similarprocess,the narrowed Si_(0.7)Ge_(0.3)channel FinFET can realize a strong gate control capability by using this newly developedwet treatment process,because its subthreshold slope can be reduced by 24%,improving from 87 mV/dec to 64 mV/dec.

关键词： Si_(0.7)Ge_(0.3) FinFET cyclic wet treatment self-limited oxidation

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New structure transistors for advanced technology node CMOS ICs

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National Science Review 2024年第3期11卷 24-41页

作者： Qingzhu Zhang Yongkui Zhang Yanna Luo Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of Chinese Academy of Sciences(IMECAS) State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Integrated Circuits University of Chinese Academy of Sciences

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits(ICs)have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor(FinFET) and gate-all-around FET(GAAFET), more gate electrodes have been added to three-dimensional(3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs(CFET), 3D stack(3DS) FETs and vertical-channel transistors(VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

关键词： transistor CMOS GAAFET CFET 3DS FET

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A Novel FinFET Device with a Four-Period Vertically Stacked SiGe/Si Fin 7

A Novel FinFET Device with a Four-Period Vertically Stacked ...

引用

7th International Conference on integrated circuits and Microsystems, ICICM 2022

作者： Zhao, Fei Li, Yongliang Integrated Circuit Advanced Process Center Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665460439

In this work, a novel four-period vertically stacked SiGe/Si FinFET is demonstrated to further boost the electrical performance of the FinFET device. The stacked SiGe/Si fin structure was fabricated successfully by developing the stacked SiGe/Si epitaxial growth and etching processes. Compared with the conventional SiGe channel FinFET, the driven current ION and ION/IOFF ratio of this novel FinFET device increased by 1.6 and 10 times, respectively. Meanwhile, its subthreshold slope (SS) was improved from 149mV/dec to 90 mV/dec. The improvement of electrical performance can be attributed to the high quality SiGe layer, increased effective channel width, and excellent surface interface properties throughout the whole fabrication process. More importantly, after employing an optimized O3 passivation technique, its SS and ION/IOFF ratio can be further improved to 75mV/dec and 5\times{10}^{6}, respectively. The above results strongly suggest that this novel stacked SiGe/Si channel FinFET device is a promising candidate for future technology nodes. © 2022 IEEE.

关键词： Etching

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