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European Conference on Solid-State circuits (ESSCIRC)

作者： ByungJun Kim Han-Gyeol Mun Kyeong-Jun Lee Jeong-Min Woo Kiseo Kang Hyunwoo Son Jae-Yoon Sim Postech Integrated Circuits and Systems Laboratory POSTECH Pohang Korea School of Electrical and Computer Engineering Cornell Tech New York NY USA Mixed-Signal IC Design Laboratory Gyeongsang National University Jinju Korea

ISBN: (数字)9798350388138

ISBN: (纸本)9798350388145

This work presents a power-efficient latticebased crypto-processor for IoT edge devices supporting both homomorphic encryption (HE) and post-quantum cryptography (PQC) algorithms. The chip incorporates a reconfigurable architecture on a unified number system to effectively reduce the size of modulo index. It also employs a power-efficient modular arithmetic block and a scheduling for pipelined processing. The implemented chip in 28 nm CMOS achieves the state-of-the-art power efficiencies both in HE and PQC.

关键词： Out of order Protocols Processor scheduling Reconfigurable architectures Cryptography Internet of Things Indexes Homomorphic encryption Arithmetic Pipeline processing

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Near-field communications:characteristics,technologies,and engineering

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Frontiers of Information Technology & Electronic engineering 2024年第12期25卷 1580-1626页

作者： Yajun ZHAO Linglong DAI Jianhua ZHANG Ran JI Mengnan JIAN Hao XUE Hongkang YU Yunqi SUN Yu LU Zidong WU Zhuo XU Jinke LI Haiyang MIAO Zhiqiang YUAN Pan TANG Jiayu SHEN Tierui GONG Haixia LIU Jiaqi HAN Qiang FENG Zhi CHEN Lingxiang LI Gang YANG Yong ZENG Cunhua PAN Wang LIU Kangda ZHI Weidong HU Yuanwei LIU Xidong MU Chau YUEN Mérouane DEBBAH Chongwen HUANG Long LI Ping ZHANG State Key Laboratory of Mobile Network and Mobile Multimedia Technology Shenzhen 518055China ZTE Corporation Beijing 100192China Department of Electronic Engineering Tsinghua UniversityBeijing 100084China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and TelecommunicationsBeijing 100876China College of Information Science and Electronic Engineering Zhejiang UniversityHangzhou 310007China Key Laboratory of High Speed Circuit Design and EMC of Ministry of Education School of Electronic EngineeringXidian UniversityXi’an 710071China Collaborative Innovation Center of Information Sensing and Understanding Xidian UniversityXi’an 710071China National Key Laboratory of Wireless Communications University of Electronic Science and Technology of ChinaChengdu 611731China National Mobile Communications Research Laboratory Southeast UniversityNanjing 210096China Purple Mountain Laboratories Nanjing 211111China School of Electrical Engineering and Computer Science Technical University of BerlinBerlin 10623Germany School of Integrated Circuits and Electronics Beijing Institute of TechnologyBeijing 100081China Department of Electrical and Electronic Engineering The University of Hong KongHong KongChina Centre for Wireless Innovation(CWI) School of ElectronicsElectrical Engineering and Computer ScienceQueen’s University BelfastBelfast BT39DTUK School of Electrical and Electronic Engineering Nanyang Technological UniversitySingapore 639798Singapore KU 6G Research Center Khalifa University of Science and TechnologyAbu DhabiUnited Arab Emirates

Near-field technology is increasingly recognized due to its transformative potential in communication systems,establishing it as a critical enabler for sixth-generation(6G)telecommunication *** paper presents a comprehensive survey of recent advancements in near-field technology ***,we explore the near-field propagation fundamentals by detailing definitions,transmission characteristics,and performance ***,we investigate various near-field channel models—deterministic,stochastic,and electromagnetic information theory based models,and review the latest progress in near-field channel testing,highlighting practical performance and *** evolving channel models,traditional mechanisms such as channel estimation,beamtraining,and codebook design require redesign and optimization to align with near-field propagation *** then introduce innovative beam designs enabled by near-field technologies,focusing on non-diffractive beams(such as Bessel and Airy)and orbital angular momentum(OAM)beams,addressing both hardware architectures and signal processing frameworks,showcasing their revolutionary potential in near-field communication ***,we highlight progress in both engineering and standardization,covering the primary 6G spectrum allocation,enabling technologies for near-field propagation,and network deployment ***,we conclude by identifying promising future research directions for near-field technology development that could significantly impact system *** comprehensive review provides a detailed understanding of the current state and potential of near-field technologies.

关键词： 6G Near-field technology Channel model Codebook Non-diffractive beams Orbital angular momentum engineering and standardization

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Dual Halogen Doping of Graphene With Chlorine and Bromine via Electrochemical Exfoliation for High-Performance Flexible Supercapacitors

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cMat 2025年第1期2卷

作者： Zi-Long Xue Qian Li Kai Wang Kai-Rui Chen Qi Zhao Cai-Xia Xu Bin-Bin Liu Institute for Advanced Interdisciplinary Research (IAIR) School of Chemistry and Chemical Engineering University of Jinan Jinan China Institute of Electrical Engineering Chinese Academy of Sciences Beijing China Department of Materials Science and Engineering National University of Singapore Singapore Singapore School of Microelectronics and Integrated Circuits (Jiangsu Key Laboratory of Semi. Dev. & IC Design Package and Test) Nantong University Nantong China

Supercapacitors attracted great attention for their expeditious charge and discharge rates and splendid cyclic stability. The doping of heteroatoms into graphene (G) can alter the electronic configuration of carbon atoms, alleviating the stacking problem of G-based materials. This work focused on a one-step green scalable electrochemical exfoliation strategy for the rapid preparation of high-quality thin-layer G nanosheets with double halogen doping. The as-made chlorine (Cl) and bromine (Br) dual-doped graphene (Cl/Br-G) nanosheets exhibited a transparent feature with a large lateral size. Density functional theoretical calculations indicated that the introduction of Cl and Br can not only enlarge the interlayer spacing of graphene but also produce the charge distribution through the formation of delocalized π bonds in the defect region. The flexible micro-supercapacitor (MSC) constructed with Cl/Br-G as the electrodes demonstrated remarkable charge storage performance and impressive mechanical flexibility. In particular, the Cl/Br-G-MSC displayed much higher specific capacitance and long-term cycling stability for 300,000 cycles compared with the single-doping counterparts. This innovative approach to dual halogen doping in G holds significant promise for energy storage, and the electrochemical exfoliation technique offers valuable insights for producing other two-dimensional layered materials.

关键词： dual-doping energy storage flexible graphene supercapacitors

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Editor-in-Chief

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IEEE Access 2024年 12卷 i-xi页

作者： Derek Abbott Sonia Aissa Anuradha Annaswamy Nirwan Ansari Jun Cai Kun-Shan Chen Yixin Chen J.-C. Chiao Ayman El-Baz Shaikh Fattah Hoay Gooi Maya Gokhale Chih-Lin Ⅰ Giuseppe Iannaccone Yumi Iwashita Bruce Jacob Abbas Jamalipour Bahram Javidi Weihua Jiang Okyay Kaynak Hulya Kirkici Germano Lambert-Torres Shengtao Li Michal Mrozowski Michele Nappi Dalma Novak Hugo Proença Yi Qian Zhihua Qu Susanto Rahardja Mehrdad Saif Ali Serpengüzel Peter H. Siegel Ashitey Trebi-Ollennu Daniela Tuninetti Ge Wang Keith A. Wear Andreas Weisshaar C. Patrick Yue Enrico Zio School of Electrical and Electronic Engineering University of Adelaide Adelaide SA Australia Institut National de la Recherche Scientifique (INRS) Québec City Canada Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA USA Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA Concordia University Montreal Canada Guilin University of Technology Guilin China Washington University St. Louis MO USA Southern Methodist University Dallas TX USA University of Louisville/Bioengineering Department Louisville KY USA Department of Electrical and Electronic Engineering Bangladesh University of Engineering and Technology Dhaka Bangladesh Nanyang Technological University Jurong West Singapore Lawrence Livermore National Laboratory Livermore CA USA China Mobile Research Institute Beijing China University of Pisa Pisa Italy NASA-JPL California Institute of Technology Pasadena CA USA Florida Polytechnic University Lakeland FL USA The University of Sydney Sydney NSW Australia University of Connecticut Storrs CT USA Nagaoka University of Technology Nagaoka Niigata Japan Department of Electrical and Electronic Engineering Boğaziçi University Istanbul Turkey University of South Alabama Mobile AL USA Gnarus Institute Itajuba Brazil Xi’an Jiaotong University Xi’an China Gdansk University of Technology Gdansk Poland University of Salerno Fisciano Italy Octane Wireless Hanover MD USA University of Beira Interior Covilhã Portugal Department of Electrical and Computer Engineering University of NebraskaLincoln Lincoln NE USA University of Central Florida Orlando Florida USA Singapore Institute of Technology 10 Dover Dr Singapore Infocomm Technology Cluster 10 Dover Dr Singapore University of Windsor Windsor Canada Department of Physics Koç University Istanbul Turkey California Institute of Technology (CalTech) Pasadena California USA NASA-JPL Mobility and Robotics Systems S

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Analytical Model for Multi-site Efficiency with Parallel to Serial test Times, Yield and Clustering

Analytical Model for Multi-site Efficiency with Parallel to ...

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IEEE VLSI test Symposium (VTS)

作者： Naveen Velamati Robert Daasch Integrated Circuits Design and Test Laboratory Electrical and Computer Engineering Portland State University

ISBN: (纸本)9781424437696

In this paper an analytical extension to the ITRS multi-site efficiency model is proposed to obtain the distribution of multi-site efficiency. Multi-site testing is becoming one of the most popular ways for test time reduction, increasing the test throughput and reducing the overall test cost. In the model, the efficiency of multi-site testing is computed from process parameters (e.g. yield, yield clustering at wafer sort), test program parameters parallel and serial test times, and multi-site count. Multi-site trade-offs and benefits to average test time are evaluated by Monte-Carlo simulations.

关键词： Multi-site testing test cost reduction Yield ramp test time reduction Average test time

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Application of non-parametric statistics of the parametric response for defect diagnosis

Application of non-parametric statistics of the parametric r...

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IEEE International test Conference

作者： R. Gudavalli W.R. Daasch P. Nigh D. Heaberlin Integrated Circuits Design and Test Laboratory Electrical and Computer Engineering Portland State University Portland OR USA Test Strategy and Development IBM Systems and Technology Group IBM Corporation Essex Junction VT USA

ISBN: (纸本)9781424448685

This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.

关键词： Parametric statistics Circuit testing Temperature integrated circuit testing System testing Fault diagnosis Inspection Scattering Displays Application software

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Analyzing the Impact of Fault-tolerant BIST for VLSI design

Analyzing the Impact of Fault-tolerant BIST for VLSI Design

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： W. Robert Daasch Saurabh Jain David Armbrust Integrated Circuits Design and Test Laboratory Department of Electrical and Computer Engineering Portland State University USA

ISBN: (纸本)9780769533650

This paper examines fault-tolerant DfT (design for test) circuits as an effective approach for improved reliability and lower defective parts per million (DPPM). The paper provides a comprehensive examination of one alternative, quadded gate, inter-leaved node logic design. Quadded DfT circuitry is compared to circuitry with no fault tolerance in terms of area, power and performance. Ever shrinking device sizes are challenging the reliability limits and testing capabilities of a modern day integrated circuit (IC). Parametric variations, higher gate counts and lower pin counts render fault avoidance techniques ineffective and make fault detection an engineering challenge. Higher defect rates and Ultra Large Scale Integration (ULSI) will require bigger and complex DfT circuitry. This will result in more chips being rejected due to DfT failures. Fault-tolerant DfT directly translates to shorter time-to-market, increased reliability and improved yield learning.

关键词： Logic gates Fault tolerance Fault tolerant systems Circuit faults Built-in self-test Libraries integrated circuit reliability

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Successful Development and Implementation of Statistical Outlier Techniques on 90nm and 65nm Process Driver Devices

Successful Development and Implementation of Statistical Out...

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Annual International Symposium on Reliability Physics

作者： Kenneth M. Butler Suresh Subramaniam Amit Nahar John M. Carulli Thomas J. Anderson W. Robert Daasch SiTD Qual. & Rel. Engineering Texas Instruments Inc. Dallas TX USA Make Operations Texas Instruments Inc. Dallas TX USA Integrated Circuits Design and Test Laboratory Electrical and Computer Engineering Portland State University Portland OR USA

Burn-in and the concomitant post-burn-in retest are significant cost adders to the overall IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit analyses with parametric or non-parametric statistics, when applied to the newest technologies, result in excessive Type I or II errors which cannot be tolerated. In this paper, we describe the results from applying statistical burn-in avoidance techniques using time-zero sort test responses to driver designs fabricated in 90nm and 65nm low leakage technologies and libraries

关键词： Automatic testing Manufacturing Delay Driver circuits Circuit testing integrated circuit testing Current measurement Power measurement Current supplies Power supplies

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Operational systems, logistics engineering and technology insertion

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NAVAL ENGINEERS JOURNAL 1997年第3期109卷 205-220页

作者： Grubb, MJ Skolnick, A Michael J. Grubb:has perfomzed naval engineering at the Crane Division Naval Surface Warfare Center (NSWC) for more than twenty-five years. He currently the program manager for the Sustainable Hardware and Affordable Readiness Practice Program (SHARP). is a Navy-wide logistics research and development prgram aimed at the successful transiton of proved technologies inot the fleet. SHARP focuses on reducing acquisition performance capability reliability maintainability and readiness of these systems. Mr. Grubb has served as a department director for the past eleven years. His most recent assignment was as director of the Tactical Computer Resources and Test Equipment Department. This organization provided acquisition and in-service engineering support of the Navy's tectical embedded computers priphirals displays and mass memory storage devices. The organization also provided a complete range of product engineering and metrology engineerig services for SSP NevSeaSysCom and the Trident Program. Prior to this appointment Mr. Grubb was deptuy director psysical security programs department and site responsible for program management and system integration of ashore integrated security systems. Mr. Grubb holds a B.S. degree in industrial engineering from Iowa State Universtiy an M.S. degree in industrial engineering from Purdue University and has copleted the course work (Dec.'96 for a master's degree in public and environment affairs at Indiana University-Purdue Univeristy Indianapolis. Dr. Alfred Skolnick operates System Science Consultants (SSC) specilizing in strategic planning technical program definiton technology assessment and engineering analyses on selected matters of national interest. He has taught physics mathematics and management sciences at University of Virginia and Marymount University and is currently adjunct professor of mathematics at Northern Virginia Community College. Form 1985 to 1989 he was president of the American Society of Noval Engineers. Dr. Skolnick served at Applied Physic

In an era of fiscal austerity, downsizing and unforgiving pressure upon human and economic capital, it is an Augean task to identify resources for fresh and creative work. The realities of the day and the practical demands of more immediate fleet needs can often dictate higher priorities. Yet, the Navy must avoid eating its seed corn. Exercising both technical insight and management foresight, the fleet, the R&D community, the Office of the Chief of Naval Operations (OpNav) and the product engineering expertise of the Naval Surface Warfare Center (NSWC) are joined and underway with integrated efforts to marry new, fully demonstrated technologies and operational urgencies. Defense funding today cannot sponsor all work that can be mission-justified over the long term because budgets are insufficient to support product maturation within the classical development cycle. However, by rigorous technical filtering and astute engineering of both marketplace capabilities and currently available components, it is possible in a few select cases to compress and, in effect, integrate advanced development (6.3), engineering development (6.4), weapon procurement (WPN), ship construction (SCN), operation and maintenance (O&M,N) budgetary categories when fleet criticalities and technology opportunities can happily meet. In short, 6.3 funds can be applied directly to ''ripe gateways'' so modern technology is inserted into existing troubled or aging systems, sidestepping the lengthy, traditional development cycle and accelerating practical payoffs to recurrent fleet problems. To produce such constructive results has required a remarkable convergence of sponsor prescience and engineering workforce excellence. The paper describes, extensively, the philosophy of approach, transition strategy, polling of fleet needs, technology assessment, and management team requirements. The process for culling and selecting specific candidate tasks for SHARP sponsorship (matching operational need with t

关键词： Naval vessels

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design AND FABRICATION OF MICROELECTROMECHANICAL SYSTEMS

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JOURNAL OF MECHANICAL design 1994年第4期116卷 1081-1088页

作者： KOTA, S ANANTHASURESH, GK CRARY, SB WISE, KD Design Laboratory Department of Mechanical Engineering and Applied Mechanics University of Michigan Ann Arbor MI 48109 Center for Integrated Sensors and Circuits Solid-State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109

An attempt has been made to summarize some of the important developments in the emerging technology of microelectromechanical systems (MEMS) from the mechanical engineering perspective. In the micro domain, design and fabrication issues are very much different from those of the macro world. The reason for this is twofold. First, the limitations of the micromachining techniques give way to new exigencies that are nonexistent in the macromachinery. One such difficulty is the virtual loss of the third dimension, since most of the microstructures are fabricated by integrated circuit based micromachining techniques that are predominantly planar. Second, the batch-produced micro structures that require no further assembly, offer significant economical advantage over their macro counterparts. Furthermore, electronic circuits and sensors can be integrated with micromechanical structures. In order to best utilize these features, it becomes necessary to establish new concepts for the design of MEMS. Alternate physical forms of the conventional joints are considered to improve the manufacturability of micromechanisms and the idea of using compliant mechanisms for micromechanical applications is put forth. The paper also reviews some of the fabrication techniques and the micromechanical I devices that have already been made. In particular, it discusses the fabrication of a motor-driven four-bar linkage using the ''boron-doped bulk-silicon dissolved- wafer I process'' developed at The University of Michigan's Center for integrated Sensors and circuits.

关键词： Micromechanical devices Semiconductor wafers Boron Mechanical engineering Linkages Dimensions integrated circuits Micromachining Electronic circuits Microelectromechanical systems circuits Compliant mechanisms Sensors Motors Silicon design Manufacturing Engines

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