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检索条件"机构=Intel - Assembly and Test Technology Development"

共 122 条记录，以下是91-100 订阅

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Performance evaluation of a sessile drop deposition process

Performance evaluation of a sessile drop deposition process

引用

28th Annual Meeting of the American Society for Precision Engineering, ASPE 2013

作者： Chesna, Jacob W Rivers, Ryan I Smith, Stuart T Samara, Ayman M Center for Precision Metrology University of North Carolina at Charlotte Charlotte NC United States Assembly and Test Technology Development Intel Chandler AZ United States

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Large angle of bragg diffraction using interfrence of acoustic wave inside acousto-optic deflector

Large angle of bragg diffraction using interfrence of acoust...

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32nd International Congress on Applications of Lasers and Electro-Optics, ICALEO 2013

作者： Wang, Tiansi Zhang, Chong Aleksov, Aleksandar Salama, Islam A Kar, Aravinda Material Science Engineering Department College of Optics and Photonics Mechanical and Aeronautical Engineering University of Central Florida P.O. Box 162700 Orlando FL 32816-2700 United States Intel - Assembly and Test Technology Development 5000 W Chandler Blvd Chandler AZ 85226 United States Intel - Components Research 5000 W Chandler Blvd Chandler AZ 85226 United States

The laser beam is often steered in different directions in a variety of laser-advanced microprocessing technologies, such as laser micromachining, laser patterning and laser selective-area doping. Scanners are traditionally used to direct the beam to different locations on the workpiece. The mechanical motion of x-y mirrors in such scanners affects the accuracy of beam positioning and repeatability in high precision manufacturing. Beam steering without any moving optical component is necessary to overcome the limitations of current scanning technology. Stationary optical devices such as acousto-optic modulators (AOM), acousto-optic deflectors (AOD) and acousto-optic tunable filters (AOTF) have widespread applications in the field of laser microfabrication for intensity modulation and laser beam steering. AODs are commonly used with continuous-wave lasers in laser direct writing systems to provide flexible and high-speed beam scanning with high precision and accuracy. A pair of AODs is mounted orthogonally to provide dual axis (x-y) laser scanning. The deflection scan angle, however, is small due to the finite distance between the two separate deflectors. This optical configuration can be simplified by realizing 2D AO interaction in a single AO crystal. This paper discusses an integrated AOD to allow compact construction and efficient operation with large deflection scan angle. This type of AODs would be useful for large-area processing with high throughput.

关键词： Continuous wave lasers

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Low-k ILD Reliability Through Chip-Package assembly: Engineering Appropriate Stress tests and Process Certification Criteria

Low-k ILD Reliability Through Chip-Package Assembly: Enginee...

引用

IEEE Electronic Components and technology Conference

作者： Sudarshan Rangaraj Jeffrey Hicks Michael O'Day Ankur Aggarwal Terri Wilson Ramanarayanan Panchapakesan Rohit Grover Guotao Wang Technology Development and Manufacturing Quality and Reliability Intel Corporation Design Technology Solutions Intel Corporation Portland Technology Development Intel Corporation Assembly and Test Technology Development Intel Corporation

ISBN: (纸本)9781479902330

Inter-layer dielectric (ILD) materials used in silicon chip backend layers tend to be mechanically fragile, and the industry trend is towards ILD materials with even lower dielectric constants and fracture toughness. Flip-chip packaging with lead-free solder materials imposes significant thermo-mechanical stresses on these fragile ILD films due to the thermal expansion miss-match between the silicon chip and organic package. To guarantee low-K ILD integrity through chip-package assembly and reliability in use with adequate margin it is crucial to understand and quantify the sources of stress, their variability and use this information to define the right stress tests and success criterion. This paper will present a systematic study of the modulators of low-K ILD stress using empirical data from 45, 32 and 22nm intel processes as well as finite element modeling. Key sources of variation in the silicon chip process as well as the chip-package assembly process will be examined and their effects on ILD stress will be quantified. This information will be used to assess the amount of over-stress needed to account for worst case manufacturing variation in silicon chip and chip - package assembly processes. Two approaches to characterization tests that provide the required over-stress will be discussed. The first approach is based on chip processing and package design skews to increase the ILD stress while the second approach relies on cooling the chip-package to below room temperature post-assembly in order to exaggerate the thermal expansion miss-match and over-stress the ILD layers. Process certification criteria to guarantee ILD reliability will be presented and optimized sampling plans to demonstrate that these goals are met will also be discussed.

关键词： ILD assembly Engineering

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Moisture absorption and hygroscopic swelling behavior of an underfill material

Moisture absorption and hygroscopic swelling behavior of an ...

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作者： He, Yi Assembly Test and Technology Development MS CH5-157 Intel Corporation 5000 W. Chandler Blvd. Chandler AZ 85226 United States

In situ moisture absorption and hygroscopic swelling behavior of an underfill material used for electronic packaging have been investigated using sorption thermogravimetric analysis (sorption TGA) and dynamic mechanical analysis (DMA) techniques under a controlled relative humidity (RH) environment. Results showed that moisture diffusion in this material can be described by Fick's diffusion law when the relative humidity is 60% or less, while at a high moisture level (85% RH), non-Fickian diffusion becomes apparent in the latter stage of the diffusion process. An increase in moisture absorption ability was observed after exposure at high temperature and high humidity level, which can be attributed to hygrothermal aging-induced damage in the material. DMA results revealed that hygroscopic swelling is significant comparing with the thermal expansion of the material. The coefficient of hygroscopic swelling (CHS) was calculated and the results showed that CHS is temperature dependent, and it increases with the increasing temperature. © 2012 Elsevier B.V. All rights reserved.

关键词： Dynamic mechanical analysis

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Thermal management of packages with 3D die stacking

Thermal management of packages with 3D die stacking

引用

International Microsystems, Packaging, assembly and Circuits technology (IMPACT)

作者： Chia-Pin Chiu Je-Young Chang Sanjoy Saha Assembly & Test Technology Development Intel Corporation Chandler AZ USA

ISBN: (纸本)9781467316354

The objective of thermal design requirement for 3D stacked die package is to maintain the junction temperatures of active devices in the package at or below specified limits. In this paper, die-to-die thermal resistance is identified as the key bottleneck in 3D thermal management, and two solution paths are proposed: fully-populated thermal bump array and thermally conductive underfill materials. The sensitivity of the thermal bump array design and the effective thermal conductivity of underfill materials will be discussed. In addition to die-to-die thermal resistance reduction, enhancement of the overall packaging cooling capability by integrating liquid cooling to the package heat spreader is another option especially for the server type of environment which typically dissipates high power. An alternative approach is to integrate thermo-electric cooling to the heat spreader for hot spot cooling. For systems that are limited to traditional air cooling, this paper will propose a different package architecture which will utilize existing cooling capability of 3D die stacking. Although the power dissipation capability of 3D die stacking is worse than the 2D multiple-chip packages, dual-die stacking can potentially achieve a higher efficiency of “performance per power” by utilizing the same concept of dual-core microprocessor. This approach is very useful especially when the package real estate is limited and 3D die stacking is the preferred package architecture.

关键词： Thermal resistance Cooling Thermal conductivity Microchannel Heating Materials

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Reducing uncertainty of wettability measurements through controlled sessile droplet deposition: Current issues

Reducing uncertainty of wettability measurements through con...

引用

27th Annual Meeting of the American Society for Precision Engineering, ASPE 2012

作者： Chesna, Jacob W. Rivers, Ryan I. Smith, Stuart T. Her, Tsing-Hua Samara, Ayman M. Center for Precision Metrology UNC Charlotte Charlotte NC United States Physics and Optical Science UNC Charlotte Charlotte NC United States Assembly and Test Technology Development Intel Chandler AZ United States

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Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

Low-k interconnect stack with metal-insulator-metal capacito...

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IEEE International Conference on Interconnect technology

作者： D. Ingerly A. Agrawal R. Ascazubi A. Blattner M. Buehler V. Chikarmane B. Choudhury F. Cinnor C. Ege C. Ganpule T. Glassman R. Grover P. Hentges J. Hicks D. Jones A. Kandas H. Khan N. Lazo K. S. Lee H. Liu A. Madhavan R. McFadden T. Mule D. Parsons P. Parthangal S. Rangaraj D. Rao J. Roesler A. Schmitz M. Sharma J. Shin Y. Shusterman N. Speer P. Tiwari G. Wang P. Yashar K. Mistry Logic Technology Development Intel Corporation Hillsboro OR USA Logic Technology Development Corporate Quality Network Intel Corporation Hillsboro OR USA Logic Technology Development Assembly Test and Technology Development Intel Corporation Hillsboro OR USA

We describe interconnect features for intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

关键词： Metals Capacitance Resistance Dielectrics Stress Integrated circuit interconnections MIM capacitors

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Probabilistic Design-for-Reliability Concept and Novel Approach to Qualification testing of Aerospace Electronic Products

Probabilistic Design-for-Reliability Concept and Novel Appro...

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IEEE Aerospace Conference

作者： E. Suhir R. Mahajan A.E. Lucero L. Bechou Bell Laboratories Physical Sciences and Engineering Research Division Murray Hill NJ (ret) University of California Santa Cruz CA Intel Corporation Assembly Pathfinding Assembly and Test Technology Development MS CH5-157 5000 West Chandler Blvd. Chandler AZ 85226 Intel Corporation Technology and Manufacturing Group MS CH5-263 5000 West Chandler Blvd. Chandler AZ 85226 University of Bordeaux 1 CNRS UMR 5218 IMS Laboratory Reliability Group 351 Cours de la Liberation 33405 Talence Cedex (F)

ISBN: (纸本)9781457705564

Qualification testing (QT) is the major means to make a viable device into a reliable product. The short-term goal of a particular electronic device manufacturer is to conduct and pass the established QT, without questioning if they are adequate. The ultimate long-term goal of electronic industries, whether aerospace, military, or commercial, regardless of a particular manufacturer or a product, is to make their deliverables reliable in the actual operations. It is well known, however, that today's electronic devices that passed the existing QT often fail in the field (in operation conditions). Are the existing QT specifications adequate? Do electronic industries need new approaches to qualify their devices into products? Could the existing QT specifications and practices be improved to an extent that if the device passed the QT, there is a quantifiable way to assure that its performance will be satisfactory? At the same time, there is a perception, perhaps, a substantiated one, that some electronic products "never fail". It is likely that such a perception exists because these products are superfluously durable, are more robust than is needed for a particular application and, as the consequence of that, are more costly than necessary. To prove that it is indeed the case, one has to find a consistent way to quantify the level of the product robustness in the field. Then one could establish if a possible and controlled reduction in the reliability level could be translated into a significant cost reduction. We suggest a concept that enables one to provide affirmative answers to the above questions. One effective way to improve the existing QT and specs is to use the probabilistic design for reliability (PDfR) approach, and based on such an approach 1) conduct the appropriate accelerated life testing (ALT), i.e., failure-oriented accelerated testing (FOAT) at both the design and the manufacturing stages, and, since ALT/FOAT cannot do without predictive modeling (PM),

关键词： failure probability electronics industry electronic products identification tests Specifications reliability criteria COST REDUCTION failure physics florentium preventive maintenance Human factors aerospace ACCELERATED testING

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Surface energy and wettability study of flip chip packaging materials

Surface energy and wettability study of flip chip packaging ...

引用

44th International Symposium on Microelectronics 2011, IMAPS 2011

作者： Wang, Jinlin Assembly Test and Technology Development Intel Corporation 5000 W. Chandler Blvd. Chandler AZ 85226 United States

ISBN: (纸本)9781618398505

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

关键词： Substrates

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In-situ characterization of moisture absorption-desorption and hygroscopic swelling behavior of an underfill material

In-situ characterization of moisture absorption-desorption a...

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Electronic Components and technology Conference (ECTC)

作者： Yi He Assembly Test & Technology Development Intel Corporation Chandler AZ USA

Moisture absorption and hygroscopic swelling behavior of an underfill material were measured in-situ using the sorption TGA and the DMA-RH techniques, respectively. Results showed that moisture diffusion can be well described by Fick's law when the relative humidity (RH) is 60% or less, and the diffusivity exhibits an Arrhenius temperature dependence with an activation energy of ~ 0.56 eV. At 85% RH, non-Fickian diffusion behavior becomes apparent in the latter stage of the diffusion process. Increase in the saturated moisture content (C sat ) at 60%RH was observed after exposure at 85°C 85%RH, which is attributed to hygrothermal ageing induced damage in the material. In-situ DMA-RH results showed that hygroscopic swelling strain is significant comparing with the thermal expansion of the material, and the swelling strain at 60°C 60%RH is equivalent to the thermal strain over a ΔT of 100°C for T g. The coefficient of hygroscopic swelling (CHS) was calculated and the results showed that CHS is temperature dependent, and it increases with the increasing temperature. At higher humidity condition (85%RH or higher), the swelling strain deviates from its linear dependence on C sat and it increases faster than linear when C sat increases, which may also be attributed to hygrothermal ageing induced damage in the underfill material.

关键词： Moisture Absorption Temperature measurement Materials Humidity Strain Temperature dependence

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