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检索条件"机构=Intel - Assembly and Test Technology Development"

共 122 条记录，以下是31-40 订阅

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Integrated Voltage Regulator Efficiency Improvement using Coaxial Magnetic Composite Core Inductors

Integrated Voltage Regulator Efficiency Improvement using Co...

引用

Electronic Components and technology Conference (ECTC)

作者： Krishna Bharath Kaladhar Radhakrishnan Michael J. Hill Prithwish Chatterjee Haifa Hariri Srikrishnan Venkataraman Huong T. Do Leigh Wojewoda Sriram Srinivasan Assembly and Test Technology Development Intel Corporation Xeon Performance Group Intel Corporation

The package integrated inductors employed by intel's Fully Integrated Voltage Regulator (FIVR) have had to scale in tandem with the circuits they power. This reduction in available volume has resulted in degraded inductor quality factor and reduced conversion efficiency. In this work, a novel coaxial magnetic composite core inductor, called Coax MIL, is described. Coax MIL dramatically improves inductor performance and quality factor. This improvement in inductor metrics translates to reduced ripple current and enhanced efficiency.

关键词： Q-factor Measurement Regulators Magnetic cores Conferences Inductors Voltage control

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Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis

Tree-Based Boosting for Efficient Estimation of S-Parameters...

引用

IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Doğanay Özese Mustafa Gökçe Baydoğan Ahmet Cemal Durgun Kemal Aygün Department of Industrial Engineering Boğaziçi University İstanbul Türkiye Department of Electrical and Electronics Engineering Middle East Technical University Ankara Türkiye Assembly and Test Technology Development Intel Corporation Chandler AZ USA

We propose a gradient boosted tree surrogate model for S-parameter prediction in high frequency structures with limited training data. Compared to data-hungry neural networks, our approach achieves reasonable accuracy... 详细信息

ISBN: (数字)9798350351231

ISBN: (纸本)9798350351248

关键词： Training Accuracy Three-dimensional displays Computational modeling Training data Artificial neural networks Data models Scattering parameters Space exploration Optimization

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Tree-Based Sequential Sampling for Efficient Designs in Package Electrical Analysis

Tree-Based Sequential Sampling for Efficient Designs in Pack...

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IEEE Workshop on Signal Propagation on Interconnects (SPI)

作者： Doğanay Özese Mustafa Gökçe Baydoğan Ahmet C. Durgun Kemal Aygün Department of Industrial Engineering Boğaziçi University İstanbul Türkiye Department of Electrical and Electronics Engineering Middle East Technical University Ankara Türkiye Assembly and Test Technology Development Intel Corporation Chandler AZ USA

ISBN: (数字)9798350382938

ISBN: (纸本)9798350382945

The use of surrogate models (SMs) has become popular in electromagnetic (EM) design and optimization. Traditional SMs, while beneficial, are often hindered by the inherent complexity and nonlinearity of EM systems, leading to challenges in data representation and design space exploration. Addressing these challenges, we introduce a novel tree-based learning strategy for sampling within high-dimensional EM design spaces. Our method emphasizes the localized exploration to accurately capture the unique output behaviors at various frequencies in multi-frequency EM simulations. The proposed method focuses on refining the sampling process instead of optimizing an objective function. The resulting strategy is a robust, nonparametric learning approach that facilitates the sequential selection of design configurations, promoting uniform accuracy in the sampled data. It also enhances the interpretability in high-dimensional spaces and provides a variable importance measure for output profile discrimination. Our empirical results show that this strategy improves the learning trajectory of SMs against random sampling from a Latin hypercube design.

关键词： Training Refining Hypercubes Extraterrestrial measurements Linear programming Feature extraction Robustness

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Determining PCIe5 Jitter Margin using SIPI Co-Sim

Determining PCIe5 Jitter Margin using SIPI Co-Sim

引用

International SoC Design Conference, ISOCC

作者： Fern Nee Tan Li Wern Chew Ling Li Ong Sze Lin Mak and Chee Hoong Mah Client System Architecture & Engineering Intel Corporation Penang Malaysia Assembly Test Technology Development Intel Corporation Penang Malaysia

ISBN: (纸本)9781665459723

This paper explores Signal Integrity Power Integrity relationship in a dual reference package design and understanding of High-Speed Interconnects circuit's behavior through Jitter Transfer Function. Using PCIe5 as a case study, a SIPI co-simulation methodology is proposed where it first decomposed the power noise into frequency spectrums and then injected these noise spectrums to the simulation testbench for dual referencing impact assessment on PCIe5 margin. Simulation results shown that the power supply induced jitter has high influence on the signaling performance at mid frequencies between 4MHz-80MHz, which is well correlated to the jitter transfer function's bandpass filter behavior of PCIe5.

关键词： Band-pass filters Sensitivity Power supplies Simulation Transfer functions Integrated circuit interconnections Receivers

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Die Embedding Challenges for EMIB Advanced Packaging technology

Die Embedding Challenges for EMIB Advanced Packaging Technol...

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Electronic Components and technology Conference (ECTC)

作者： Gang Duan Yosuke Kanaoka Robin McRee Bai Nie Rahul Manepalli Substrate Packaging Technology Development Assembly & Test Technology Development Intel Corporation Chandler AZ USA

intel's Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnects of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. This technology uses local silicon bridges to host ultrafine line / space structures for die-to-die interconnect communications and opens avenues for heterogeneous chip integration applications. In EMIB package architecture, a silicon bridge die is embedded into an organic substrate, encapsulated with dielectric materials, and connected to external layers of package substrate through semi additive substrate build-up processes at the panel level. Many bridge dice can be embedded as part of the high-density interconnect package substrate fabrication process. Afterwards, logic or heterogeneous dice (Chiplets of various nodes / sources, HBMs, IO tiles, etc.) are bonded to EMIB substrates through assembly process, with EMIB bridges serving as a high-bandwidth, low-latency, and low-power solution for die-to-die communications, thereby enabling a low-cost, highperformance in-package heterogeneous chip integration solution. Simply put, EMIB employs a silicon piece that hosts ultrafine line / space structures, fabricated with silicon far-backend technology, but out of intel's high-density interconnect package substrate manufacturing infrastructures and capabilities. One of the key elements of EMIB advanced packaging technology is to embed the EMIB bridge dice reliably during the substrate fabrication process. As such, an overview of the general technical challenges associated with panel level EMIB die embedding will be presented in this paper as compared to the industry standard wafer level packaging (WLP) die embedding process.

关键词： Bridges Fabrication Semiconductor device reliability Packaging Throughput Silicon Wafer scale integration

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Enabling Next Generation 3D Heterogeneous Integration Architectures on intel Process

Enabling Next Generation 3D Heterogeneous Integration Archit...

引用

International Electron Devices Meeting (IEDM)

作者： A. Elsherbini K. Jun S. Liff T. Talukdar J. Bielefeld W. Li R. Vreeland H. Niazi B. Rawlings T. Ajayi N. Tsunoda T. Hoff C. Woods G. Pasdast S. Tiagaraj E. Kabir Y. Shi W. Brezinski R. Jordan J. Ng X. Brun B. Krisnatreya P. Liu B. Zhang Z. Qian M. Goel J. Swan G. Yin C. Pelto J. Torres P. Fischer Components Research Logic Technology Development Assembly and Test Technology Development Design Engineering Group Corporate Quality Network Global Sourcing for Equipment and Materials Design Enabling Group Intel Corporation USA

ISBN: (纸本)9781665489607

This paper discusses a new generation of heterogeneous integration architectures which we refer to as quasi-monolithic chips (QMC). QMC enables flexible out-of-order combinations of silicon process & packaging techniques to create flexible and ultra-high interconnect density 3D architectures to fit future computing & AI needs. We show the main structural elements of the architecture and its performance including up to 10X interconnect power reduction and density improvements. We also cover the main new process modules needed to enable QMC including high density back-end compatible hybrid bonding and ultra-thick oxide fill modules.

关键词： Three-dimensional displays Optical imaging Silicon Hybrid power systems Dielectrics Optical films Bonding

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A Flexible Neural Network-Based Tool for Package Second Level Interconnect Modeling

A Flexible Neural Network-Based Tool for Package Second Leve...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Furkan Karatoprak Ekin Su Saçın Doǧanay Özese Ahmet C. Durgun Mustafa Gökçe Baydoǧan Kemal Aygün Tolga Memioǧlu Department of Electrical and Electronics Engineering Middle East Technical University Ankara Türkiye Department of Industrial Engineering Boǧaziçi University İstanbul Türkiye Assembly and Test Technology Development Intel Corporation Chandler AZ USA

This paper introduces a neural network (NN)-based practical design tool for quick assessment of package second level interconnects (SLIs) at the earlier design stages. The study addresses the well-known computational cost problem of data generation and training processes of NN implementation by proposing a flexible model approach, where the SLI geometry is divided into several building blocks, for which a separate NN model was trained. The NNs take geometrical parameters as inputs and return the complex S-parameter matrices as outputs. The electrical performance of the entire SLI geometry is obtained by cascading the S-paramaters of the building blocks.

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Cold Spray: A Disruptive technology for Enabling Novel Packaging Thermomechanical Solutions

Cold Spray: A Disruptive Technology for Enabling Novel Packa...

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Electronic Components and technology Conference (ECTC)

作者： Feras Eid Aastha Uppal Johanna Swan Components Research Intel Corporation Chandler AZ USA Assembly Test Technology Development Intel Corporation Chandler AZ USA

This paper presents cold spray as a nascent semiconductor packaging capability with promising thermomechanical applications. Cold spray enables fast, low temperature, solid-state additive manufacturing of die backside coatings with near-bulk properties and low contact resistances. With appropriate process and material optimization, those coatings can reduce package warpage at reflow temperatures and improve heat spreading from die hotspots, enabling higher processor power and performance. Experiments and simulations are presented which demonstrate the advantages of the proposed die backside cold spray architecture and the breakthrough capabilities of the cold spray process itself, positioning cold spray as a powerful new packaging tool with far-reaching potential.

关键词： Heating systems Micrometers Temperature Thermal resistance Thermomechanical processes Packaging Tools

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Hybrid Bonding Interconnect for Advanced Heterogeneously Integrated Processors

Hybrid Bonding Interconnect for Advanced Heterogeneously Int...

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Electronic Components and technology Conference (ECTC)

作者： Adel Elsherbini Shawna Liff Johanna Swan Kimin Jun Sathya Tiagaraj Gerald Pasdast Technology Development - Components Research Intel Corporation Chandler AZ Assembly & Test Technology Development Intel Corporation Chandler AZ Design Engineering Group Intel Corporation Santa Clara CA

Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology, hybrid bonding, removes many of these limitations and allows several order of magnitude improvements in die-to-die connection density. In this paper, we provide an overview of hybrid bonding technology and its capabilities in the context of high-performance computing applications. The basic process & benefits of hybrid bonding vs. conventional solder interconnect are discussed. The signal integrity and power reduction benefits of hybrid bonding for several types of die-to-die interconnects are shown. We demonstrate that hybrid bonding can decrease the interconnect parasitics & correspondingly reduce the interconnect power by more than 5X. The design, manufacturing & assembly steps of our test chips and some of the fabrication results are also discussed.

关键词： Fabrication Program processors Conferences Stacking Integrated circuit interconnections Electronic components Hybrid power systems

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Enabling Hybrid Bonding on intel Process

Enabling Hybrid Bonding on Intel Process

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International Electron Devices Meeting (IEDM)

作者： Adel Elsherbini Kimin Jun Richard Vreeland William Brezinski Haris Khan Niazi Yi Shi Qiang Yu Zhiguo Qian Jessica Xu Shawna Liff Johanna Swan Jimin Yao Pilin Liu Christopher Pelto Said Rami Ajay Balankutty Paul Fischer Bob Turkot Components Research Intel Corporation USA Assembly and Test Technology Development Intel Corporation USA Design Enablement Intel Corporation USA Corporate Quality Network Intel Corporation USA Logic Technology Development Intel Corporation USA

ISBN: (纸本)9781665425735

In this paper, we holistically discuss the recent design, wafer fabrication and die assembly changes needed to enable hybrid bonding interconnect (HBI) on intel process. HBI enables orders of magnitude improved interconnect density compared to solder which opens the doors to many new 3D packaging architectures. Starting with the design aspect, we show the physical interconnect changes that results in much lower parasitics. We also show the impacts on the top metal layer passives and power delivery and how to minimize these impacts through specific design changes. Afterwards, the wafer fabrication process changes are shown such as the fabrication of the bonding metal layers without causing excessive wafer warpage and the optimization of the chemical mechanical polishing process to enable smooth and flat surface dielectric and controlled-recess bonding pads. The assembly process changes are also summarized with special emphasis on the need for extremely clean die surface, high accuracy die placement and maximized test coverage. Finally, we show the design, fabrication, assembly and test results of active and passive test chips utilizing intel advanced node process.

关键词： Fabrication Surface cleaning Three-dimensional displays Temperature Metals Process control Packaging

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