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IEEE International parallel and Distributed Processing Symposium

作者： Tyler M. Smith Robert van de Geijn Mikhail Smelyanskiy Jeff R. Hammond Field G. Van Zee Institute for Computational Engineering and Sciences and Department of Computer Science The University of Texas at Austin Parallel Computing Lab Intel Corporation Leadership Computing Facility Argonne National Lab

ISBN: (纸本)9781479938018

BLIS is a new framework for rapid instantiation of the BLAS. We describe how BLIS extends the "GotoBLAS approach" to implementing matrix multiplication (GEMM). While GEMM was previously implemented as three loops around an inner kernel, BLIS exposes two additional loops within that inner kernel, casting the computation in terms of the BLIS micro-kernel so that porting GEMM becomes a matter of customizing this micro-kernel for a given architecture. We discuss how this facilitates a finer level of parallelism that greatly simplifies the multithreading of GEMM as well as additional opportunities for parallelizing multiple loops. Specifically, we show that with the advent of many-core architectures such as the IBM PowerPC A2 processor (used by Blue Gene/Q) and the intel Xeon Phi processor, parallelizing both within and around the inner kernel, as the BLIS approach supports, is not only convenient, but also necessary for scalability. The resulting implementations deliver what we believe to be the best open source performance for these architectures, achieving both impressive performance and excellent scalability.

关键词： Linear algebra Libraries High-performance Matrix BLAS Multicore

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Versatile and scalable parallel histogram construction

Versatile and scalable parallel histogram construction

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International Conference on parallel Architecture and Compilation Techniques (PACT)

作者： Wookeun Jung Jongsoo Park Jaejin Lee Department of Computer Science and Engineering Seoul National University Seoul Korea Intel Corporation Parallel Computing Lab California USA

ISBN: (纸本)9781509066070

Histograms are used in various fields to quickly profile the distribution of a large amount of data. However, it is challenging to efficiently utilize abundant parallel resources in modern processors for histogram construction. To make matters worse, the most efficient implementation varies depending on input parameters (e.g., input distribution, number of bins, and data type) or architecture parameters (e.g., cache capacity and SIMD width). This paper presents versatile histogram methods that achiev competitive performance across a wide range of input types and target architectures. Our open source implementations are highly optimized for various cases and are scalable for more threads and wider SIMD units. We also show that histogram construction can be significantly accelerated by intel ® Xeon Phi coprocessors for common input data sets because of their compute power from many cores and instructions for efficient vectorization, such as gather-scatter. For histograms with 256 fixed-width bins, a dual-socket 8-core intel ® Xeon ® E5-2690 achieves 13 billion bin updates per second (GUPS), while a 60-core intel ® Xeon Phi 5110P coprocessor achieves 18 GUPS for a skewed input. For histograms with 256 variable-width bins, the Xeon processor achieves 4.7 GUPS, while the Xeon Phi coprocessor achieves 9.7 GUPS for a skewed input. For text histogram, or word count, the Xeon processor achieves 342.4 million words per seconds (MWPS). This is 4.12×, 3.46× faster than PHOENIX and TBB. The Xeon phi processor achieves 401.4 MWPS, which is 1.17× faster than the Xeon processor. Since histogram construction captures essential characteristics of more general reduction-heavy operations, our approach can be extended to other settings.

关键词： Histograms Instruction sets Computer architecture Hardware parallel processing Coprocessors

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parallel Mutual Information Based Construction of Whole-Genome Networks on the intel (R) Xeon Phi (TM) Coprocessor

Parallel Mutual Information Based Construction of Whole-Geno...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： Sanchit Misra Kiran Pamnany Srinivas Aluru Parallel Computing Lab Intel Corporation Bangalore India School of Computational Science and Engineering Georgia Institute of Technology Atlanta USA

Construction of whole-genome networks from large-scale gene expression data is an important problem in systems biology. While several techniques have been developed, most cannot handle network reconstruction at the whole-genome scale, and the few that can, require large clusters. In this paper, we present a solution on the intel (R) Xeon Phi (TM) coprocessor, taking advantage of its multi-level parallelism including many x86-based cores, multiple threads per core, and vector processing units. We also present a solution on the intel (R) Xeon (R) processor. Our solution is based on TINGe, a fast parallel network reconstruction technique that uses mutual information and permutation testing for assessing statistical significance. We demonstrate the first ever inference of a plant whole genome regulatory network on a single chip by constructing a 15,575 gene network of the plant Arabidopsis thaliana from 3,137 microarray experiments in only 22 minutes. In addition, our optimization for parallelizing mutual information computation on the intel Xeon Phi coprocessor holds out lessons that are applicable to other domains.

关键词： Vectors Joints Coprocessors Mutual information Optimization Splines (mathematics) Arrays

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Improving Communication Performance and Scalability of Native Applications on intel Xeon Phi Coprocessor Clusters

Improving Communication Performance and Scalability of Nativ...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： Karthikeyan Vaidyanathan Kiran Pamnany Dhiraj D. Kalamkar Alexander Heinecke Mikhail Smelyanskiy Jongsoo Park Daehyun Kim Aniruddha Shet G. Bharat Kaul Balint Joo Pradeep Dubey Parallel Computing Lab Intel Corporation Bangalore India Department of Informatics Technische Universitiit Miinchen Munich Germany Intel Corp Santa Clara CA US Parallel Computing Lab Intel Corporation Santa Clara CA U.S.A Thomas Jefferson National Accelerator Facility Newport News VA U.S.A

ISBN: (纸本)9781479938018

intel Xeon Phi coprocessor-based clusters offer high compute and memory performance for parallel workloads and also support direct network access. Many real world applications are significantly impacted by network characteristics and to maximize the performance of such applications on these clusters, it is particularly important to effectively saturate network bandwidth and/or hide communications latency. We demonstrate how to do so using techniques such as pipelined DMAs for data transfer, dynamic chunk sizing, and better asynchronous progress. We also show a method for, and the impact of avoiding serialization and maximizing parallelism during application communication phases. Additionally, we apply application optimizations focused on balancing computation and communication in order to hide communication latency and improve utilization of cores and of network bandwidth. We demonstrate the impact of our techniques on three well known and highly optimized HPC kernels running natively on the intel Xeon Phi coprocessor. For the Wilson-Dslash operator from Lattice QCD, we characterize the improvements from each of our optimizations for communication performance, apply our method for maximizing concurrency during communication phases, and show an overall 48% improvement from our previously best published result. For HPL/LINPACK, we show 68.5% efficiency with 97 TFLOPs on 128 intel Xeon Phi coprocessors, the first ever reported native HPL efficiency on a coprocessor-based supercomputer. For FFT, we show 10.8 TFLOPs using 1024 intel Xeon Phi coprocessors on the TACC Stampede cluster, the highest reported performance on any intel Architecture-based cluster and the first such result to be reported on a coprocessor-based supercomputer.

关键词： Message systems Coprocessors Bandwidth Lattices Optimization parallel processing Kernel

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WorkQ: A many-core producer/consumer execution model applied to PGAS computations

WorkQ: A many-core producer/consumer execution model applied...

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International Conference on parallel and Distributed Systems (ICPADS)

作者： David Ozog Allen Malony Jeff R. Hammond Pavan Balaji Dept. of Computer and Information Science University of Oregon Eugene Oregon Parallel Computing Lab Intel Corporation Hillsboro Oregon Math. and Computer Science Div. Argonne National Laboratory Lemont Illinois

ISBN: (纸本)9781479976164

Partitioned global address space (PGAS) applications, such as the Tensor Contraction Engine (TCE) in NWChem, often apply a one-process-per-core mapping in which each process iterates through the following work-processing cycle: (1) determine a work-item dynamically, (2) get data via one-sided operations on remote blocks, (3) perform computation on the data locally, (4) put (or accumulate) resultant data into an appropriate remote location, and (5) repeat the cycle. However, this simple flow of execution does not effectively hide communication latency costs despite the opportunities for making asynchronous progress. Utilizing nonblocking communication calls is not sufficient unless care is taken to efficiently manage a responsive queue of outstanding communication requests. This paper presents a new runtime model and its library implementation for managing tunable “work queues” in PGAS applications. Our runtime execution model, called WorkQ, assigns some number of on-node “producer” processes to primarily do communication (steps 1, 2, 4, and 5) and the other “consumer” processes to do computation (step 3); but processes can switch roles dynamically for the sake of performance. Load balance, synchronization, and overlap of communication and computation are facilitated by a tunable nodewise FIFO message queue protocol. Our WorkQ library implementation enables an MPI+X hybrid programming model where the X comprises SysV message queues and the user's choice of SysV, POSIX, and MPI shared memory. We develop a simplified software mini-application that mimics the performance behavior of the TCE at arbitrary scale, and we show that the WorkQ engine outperforms the original model by about a factor of 2. We also show performance improvement in the TCE coupled cluster module of NWChem.

关键词： Computational modeling Libraries Tensile stress Load modeling Electronics packaging Engines Runtime

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Lattice QCD on intel® Xeon Phi™ coprocessors

Lattice QCD on Intel® Xeon Phi™ coprocessors

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28th International Supercomputing Conference on Supercomputing, ISC 2013

作者： Joó, Bálint Kalamkar, Dhiraj D. Vaidyanathan, Karthikeyan Smelyanskiy, Mikhail Pamnany, Kiran Lee, Victor W. Dubey, Pradeep Watson III, William Thomas Jefferson National Accelerator Facility Newport News VA United States Parallel Computing Lab. Intel Corporation Bangalore India Parallel Computing Lab. Intel Corporation Santa Clara CA United States

ISBN: (纸本)9783642387494

Lattice Quantum Chromodynamics (LQCD) is currently the only known model independent, non perturbative computational method for calculations in the theory of the strong interactions, and is of importance in studies of nuclear and high energy physics. LQCD codes use large fractions of supercomputing cycles worldwide and are often amongst the first to be ported to new high performance computing architectures. The recently released intel Xeon Phi architecture from intel Corporation features parallelism at the level of many x86-based cores, multiple threads per core, and vector processing units. In this contribution, we describe our experiences with optimizing a key LQCD kernel for the Xeon Phi architecture. On a single node, using single precision, our Dslash kernel sustains a performance of up to 320 GFLOPS, while our Conjugate Gradients solver sustains up to 237 GFLOPS. Furthermore we demonstrate a fully 'native' multi-node LQCD implementation running entirely on KNC nodes with minimum involvement of the host CPU. Our multi-node implementation of the solver has been strong scaled to 3.9 TFLOPS on 32 KNCs. © 2013 Springer-Verlag.

关键词： Quantum theory

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parallel Bayesian Network Structure Learning for Genome-Scale Gene Networks

Parallel Bayesian Network Structure Learning for Genome-Scal...

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Supercomputing Conference

作者： Sanchit Misra Md. Vasimuddin Kiran Pamnany Sriram P. Chockalingam Yong Dong Min Xie Maneesha R. Aluru Srinivas Aluru Parallel Computing Lab Intel Corporation Bangalore India Dept. of Computer Science and Engineering Indian Institute of Technology Bombay Mumbai India State Key Laboratory of High Performance Computing National University of Defense Technology Changsha China School of Biology Georgia Institute of Technology Atlanta USA School of Computational Science and Engineering Georgia Institute of Technology Atlanta USA

Learning Bayesian networks is NP-hard. Even with recent progress in heuristic and parallel algorithms, modeling capabilities still fall short of the scale of the problems encountered. In this paper, we present a massively parallel method for Bayesian network structure learning, and demonstrate its capability by constructing genome-scale gene networks of the model plant Arabidopsis thaliana from over 168.5 million gene expression values. We report strong scaling efficiency of 75% and demonstrate scaling to 1.57 million cores of the Tianhe-2 supercomputer. Our results constitute three and five orders of magnitude increase over previously published results in the scale of data analyzed and computations performed, respectively. We achieve this through algorithmic innovations, using efficient techniques to distribute work across all compute nodes, all available processors and coprocessors on each node, all available threads on each processor and coprocessor, and vectorization techniques to maximize single thread performance.

关键词： Bayes methods Hypercubes Instruction sets Genomics Bioinformatics Coprocessors Vectors

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Efficient sparse matrix-vector multiplication on x86-based many-core processors 13

Efficient sparse matrix-vector multiplication on x86-based m...

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27th ACM International Conference on Supercomputing, ICS 2013

作者： Liu, Xing Smelyanskiy, Mikhail Chow, Edmond Dubey, Pradeep School of Computational Science and Engineering Georgia Institute of Technology Atlanta GA United States Parallel Computing Lab. Intel Corporation Santa Clara CA United States

ISBN: (纸本)9781450321303

Sparse matrix-vector multiplication (SpMV) is an important kernel in many scientific applications and is known to be memory bandwidth limited. On modern processors with wide SIMD and large numbers of cores, we identify and address several bottlenecks which may limit performance even before memory bandwidth: (a) low SIMD efficiency due to sparsity, (b) overhead due to irregular memory accesses, and (c) load-imbalance due to non-uniform matrix structures. We describe an efficient implementation of SpMV on the intel® Xeon Phi™ Coprocessor, codenamed Knights Corner (KNC), that addresses the above challenges. Our implementation exploits the salient architectural features of KNC, such as large caches and hardware support for irregular memory accesses. By using a specialized data structure with careful load balancing, we attain performance on average close to 90% of KNC's achievable memory bandwidth on a diverse set of sparse matrices. Furthermore, we demonstrate that our implementation is 3.52x and 1.32x faster, respectively, than the best available implementations on dual intel® Xeon™ Processor E5-2680 and the NVIDIA Tesla K20X architecture. © 2013 ACM.

关键词： Bandwidth

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Data structure and movement for lattice-based simulations

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Physical Review E 2013年第1期88卷 013314-013314页

作者： Aniruddha G. Shet Shahajhan H. Sorathiya Siddharth Krithivasan Anand M. Deshpande Bharat Kaul Sunil D. Sherlekar Santosh Ansumali Parallel Computing Lab Intel Labs Bangalore 560103 India Engineering Mechanics Unit Jawaharlal Nehru Centre for Advanced Scientific Research Jakkur Bangalore 560064 India

We show that for the lattice Boltzmann model, the existing paradigm in computer science for the choice of the data structure is suboptimal. In this paper we use the requirements of physical symmetry necessary for recovering hydrodynamics in the lattice Boltzmann description to propose a hybrid data layout for the method. This hybrid data structure, which we call a structure of an array of structures, is shown to be optimal for the lattice Boltzmann model. Finally, the possible advantages of establishing a connection between group theoretic symmetry requirements and the construction of the data structure is discussed in the broader context of grid-based methods.

关键词： DATA structures (Computer science) LATTICE theory SIMULATION methods & models LATTICE Boltzmann methods HYDRODYNAMICS COMPUTATIONAL grids (Computer systems)

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GPP-grep: High-speed regular expression processing engine on general purpose processors

GPP-grep: High-speed regular expression processing engine on...

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15th International Symposium on Research in Attacks, Intrusions, and Defenses, RAID 2012

作者： Valgenti, Victor C. Chhugani, Jatin Sun, Yan Satish, Nadathur Kim, Min Sik Kim, Changkyu Dubey, Pradeep School of EECS Washington State University United States Parallel Computing Lab. Intel Corporation United States

ISBN: (纸本)9783642333378

Deep Packet Inspection (DPI) serves as a major tool for Network Intrusion Detection Systems (NIDS) for matching datagram payloads to a set of known patterns that indicate suspicious or malicious behavior. Regular expressions offer rich context for describing these patterns. Unfortunately, large rule sets containing thousands of patterns coupled with high link-speeds leave most regular expression matching methods incapable of matching at real-time without specialized hardware. We present GPP-grep, an NFA-based regular expression processing engine designed for maximum performance on General Purpose Processors. The primary contribution of GPP-grep is the utilization of the data-level parallelism available in modern CPUs to reduce the overhead incurred when tracking multiple states in NFA. In essence, we build and store the NFA in an architecture-friendly manner that exploits locality and then traverse the NFA maximizing the parallelism available and minimizing cache-misses and long-latency memory lookups. GPPgrep demonstrates 24-57x improvement in throughput over standard finite automata techniques on a set of up to 1200 regular-expressions culled from the NIDS Snort, and is within 1.3x of FPGA hardware-based techniques. GPP-grep achieves 2Gbps throughput on a dual-socket commodity CPU system allowing for line-speed evaluation on commodity hardware. © 2012 Springer-Verlag.

关键词： Program processors

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