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Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Accurate, scalable and informative design space exploration ...

引用

International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Chang-Burm Cho James Poe Tao Li Jingling Yuan Intelligent Design of Efficient Architecture Lab IDEAL Department of ECE University of Florida Gainesville FL USA Computer Science and Technology School Wuhan University of Technology Wuhan China

ISBN: (纸本)9781424449279

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.

关键词： Space exploration Predictive models Network-on-a-chip design methodology Microprocessors Time to market Large-scale systems Analytical models Wavelet analysis Multiresolution analysis

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Modeling and Analyzing the Effect of Microarchitecture design Parameters on Microprocessor Soft Error Vulnerability

Modeling and Analyzing the Effect of Microarchitecture Desig...

引用

International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Chang Burm Cho Wangyuan Zhang Tao Li Intelligent Design of Efficient Architecture Lab(IDEAL) Department of ECE University of Florida USA

High performance and reliability are essential for microprocessor design. As semiconductor processing technology continues to move toward smaller and denser transistors, lower threshold voltages and tighter noise margins, microprocessors are becoming more susceptible to transient faults (soft errors) that can affect reliability. The increasing chip soft error rates make it is necessary to estimate process transient fault susceptibility at the microarchitecture design stage. Therefore, it becomes important to understand and to evaluate the implications of design choices and optimizations from both performance and reliability perspectives. This paper explores using predictive models to analyze and forecast the effect of various processor microarchitecture design parameters on reliability and their tradeoffs with performance. The most significant factors affecting microarchitecture structures and processor reliability and its runtime variation are obtained. Experimental results show that the proposed modeling techniques can accurately estimate processor reliability, runtime variation, and the performance/reliability tradeoffs in the early stages of microarchitecture design exploration.

关键词： Microarchitecture Microprocessors Semiconductor process modeling Runtime Threshold voltage Semiconductor device noise Semiconductor device reliability Error analysis design optimization Predictive models

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Using Analytical Models to efficiently Explore Hardware Transactional Memory and Multi-Core Co-design

Using Analytical Models to Efficiently Explore Hardware Tran...

引用

International Symposium on Computer architecture and High Performance Computing (SBAC-PAD)

作者： James Poe Chang-Burm Cho Tao Li Intelligent Design of Efficient Architecture Lab (IDEAL) Department of Electrical and Computer Engineering University of Florida USA

Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to characterize the interaction between hardware transactional memory (HTM) design dimensions and multi-core microarchitecture configuration. In this paper, we investigate the use of analytical modeling techniques to build application-specific performance models for understanding the interaction between HTM and multi-core configurations across large design points and for efficiently exploring the co-design space between the two. A key feature of our modeling technique is the ability to simultaneously capture the individual and combinatorial effects of important HTM design dimensions and core microarchitectural parameters. We show that analytical models can be effective tools for assisting architects in identifying these key effects and the interactions between HTM and multi-core microarchitecture that have a high impact on the performance of transactional memory workloads. The models also enable accurate performance prediction across the joint TM/multi-core design space. By analyzing the regression trees generated from our neural network model building methods, we further reveal heterogeneous interaction between TM workloads, core microarchitectures and TM mechanisms.

关键词： Analytical models Hardware Microarchitecture Space exploration Parallel programming Multicore processing Performance analysis Predictive models Regression tree analysis Neural networks

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Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase Analysis

Using Wavelet Domain Workload Execution Characteristics to I...

引用

IEEE International Symposium on Performance Analysis of Systems and Software

作者： Chang-Burm Cho Tao Li Intelligent Design of Efficient Architecture Lab(IDEAL) Department of ECE University of Florida USA

ISBN: (纸本)1424410819

Program phase analysis has many applications in computer architecture design and optimization. Recently, there has been a growing interest in employing wavelets as a tool for phase analysis. Nevertheless, the examined scope of workload characteristics and the explored benefits due to wavelet-based analysis are quite limited. This work further extends prior research by applying wavelets analysis to abundant types of program execution statistics and quantifying the benefits of wavelet analysis in terms of accuracy, scalability and robustness in phase classification. Experimental results on SPEC CPU 2000 benchmarks show that compared with methods that work in the time domain, wavelet domain phase analysis achieves higher accuracy and exhibits superior scalability and robustness. We examine and contrast the effectiveness of applying wavelets to a wide range of runtime workload execution characteristics. We find that wavelet transform significantly reduces temporal dependence in the sampled workload statistics and therefore simple models which are insufficient in the time domain become quite accurate in the wavelet domain. More attractively, we show that different types of workload execution characteristics in wavelet domain can be assembled together to further improve phase classification accuracy. For long-running, complex and real-world workloads, a scalable phase analysis technique is essential to capture the manifested large-scale program behavior. In this study, we show that such scalability can be achieved by applying wavelet analysis of high dimension sampled workload statistics to alleviate the counter overflow problem which can negatively affect phase classification accuracy. By exploiting the wavelet denoising capability, we show in this paper that phase classification can be performed robustly under program execution variability. To our knowledge, this work presents the first effort on using wavelets to improve scalability and robustness in phase analysis

关键词： Wavelet analysis Wavelet domain Scalability Robustness Statistical analysis Application software Computer architecture design optimization Time domain analysis Runtime

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Characterizing the Effect of Microarchitecture design Parameters on Workload Dynamic Behavior

Characterizing the Effect of Microarchitecture Design Parame...

引用

IEEE International Workshop/Symposium on Workload Characterization

作者： Chang-Burm Cho Wangyuan Zhang Tao Li Intelligent Design of Efficient Architecture Laboratory (IDEAL) Department of ECE University of Florida USA

Program runtime behavior exhibits significant variations across multiple scales. The increasing design complexity and technology scaling make microprocessor performance and efficiency increasingly depend on runtime workload dynamics. Therefore understanding the effect of design parameters on workload dynamics at early, microarchitecture exploration stage is crucial for high-performance and complexity-efficient designs. In this study, we apply wavelet-based analysis to decompose workload dynamics into a series of wavelet coefficients, which represent program behavior ranging from low-resolution approximation to high-resolution detail. We then construct error-bounded linear regression models that relate microarchitecture design parameters to various wavelet coefficients that capture workload dynamics at multiresolution levels. The most significant factors affecting program dynamics at different scales are obtained. To our knowledge, this paper presents the first work on microarchitecture design space exploration focusing on workload dynamics.

关键词： Microarchitecture Runtime Wavelet coefficients Wavelet analysis Linear regression Wavelet transforms Microprocessors Out of order Process design Space exploration

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Informed Microarchitecture design Space Exploration Using Workload Dynamics 40

Informed Microarchitecture Design Space Exploration Using Wo...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Chang-Burm Cho Wangyuan Zhang Tao Li Intelligent Design of Efficient Architecture Laboratory(IDEAL) Department of ECE University of Florida USA

ISBN: (纸本)9780769530475

Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with workload dynamics. Moreover, with the approaching billion-transistor microprocessor era, it is not always economical or feasible to design processors with thermal cooling and reliability redundancy capabilities that target an application's worst case scenario. Therefore, analyzing complex workload dynamics early, at the microarchitecture design stage, is crucial to forecast workload runtime behavior across architecture design alternatives and evaluate the efficiency of workload scenario- based architecture optimizations. Existing methods focus exclusively on predicting aggregated workload behavior. In this paper, we propose accurate and efficient techniques and models to reason about workload dynamics across the microarchitecture design space without using detailed cycle- level simulations. Our proposed techniques employ wavelet- based multiresolution decomposition and neural network based non-linear regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting performance, power and reliability domain workload dynamics that the SPEC CPU 2000 benchmarks manifest on high-performance microprocessors with a microarchitecture design space that consists of 9 key parameters. Our results show that the models achieve high accuracy in revealing workload dynamic behavior across a large microarchitecture design space. We also demonstrate that the proposed techniques can be used to efficiently explore workload scenario-driven architecture optimizations.

关键词： Microarchitecture Space exploration Microprocessors Runtime Economic forecasting Power generation economics Process design Cooling Redundancy design optimization

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