Fabrication process of 0.1μm MOSFET's were developed with Super Self-aligned ultra-Shallow junction Electrode(S3EMOSFET) by utilizing in-situ impurity doped Si1-xGex selective epitaxy on the source/drain regions ...
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ISBN:
(纸本)2863322214
Fabrication process of 0.1μm MOSFET's were developed with Super Self-aligned ultra-Shallow junction Electrode(S3EMOSFET) by utilizing in-situ impurity doped Si1-xGex selective epitaxy on the source/drain regions at 550°C by CVD. Normal saturation characteristics were observed and the threshold voltage scarcely showed a shift with the gate length, which means that the short channel effect is greatly suppressed in the S3EMOSFET. Further improvements of the current drivability were performed by annealing and selective tungsten growth. The results show very high potentials of this device for an ultrasmall MOSFET, because the effective channel length is almost the same as the fabricated gate length and the source/drain junctions are extremely shallow.
A number of two-dimensional LSIs (2D-LSIs) with the thickness of around 30 /spl mu/m which amplify and convert image signals and perform some arithmetic operations are integrated vertically in order to achieve a real-...
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A number of two-dimensional LSIs (2D-LSIs) with the thickness of around 30 /spl mu/m which amplify and convert image signals and perform some arithmetic operations are integrated vertically in order to achieve a real-time microvision system. This microvision system transfers the two-dimensional (2D) image data arrays as it is using high density vertical interconnections. So, the image information signals are processed in parallel in each LSI and the processings are performed in pipelines over all the system. In this study we design the test chip which performs edge detection by Laplacian operator. In CAD simulation, the processing time of the edge detection takes about 10 /spl mu/sec using 2 /spl mu/m CMOS design rule. In fabrication, grinding and chemical-mechanical polishing techniques are used to thin the wafer to 30 /spl mu/m. The thinned wafer with buried interconnections is bonded vertically to a thick wafer through micro-bumps after careful alignment by the newly developed wafer aligner with the alignment tolerance of 1 /spl mu/m. The microvision system with 3D integration structure can be fabricated by repeating such sequences.
Hybrid continuous-time and discrete-event system models are developed for applications to intelligent robot and autonomous control systems. Certain general properties, including the interface structure between the dis...
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Hybrid continuous-time and discrete-event system models are developed for applications to intelligent robot and autonomous control systems. Certain general properties, including the interface structure between the discrete event part and the continuous part of hybrid systems, are studied. Petri nets are proposed as the model for the discrete event sub-system (DES), and state equations with a set of binary parameters as the model for the continuous time sub-system (CTS) in a hybrid system. The quantized CTS is formulated in prime event structures, which can also be modeled by a condition/event Petri net. Therefore, a complete hybrid system can be fit into an extended Petri net formalism, which provides a unified framework for hybrid system description. The validity of the proposed model is demonstrated by modeling a two-tank system.
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