This paper presents a low noise amplifier(LNA),which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm RF-CMOS *** circuit was analyzed and a new optimization method for...
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This paper presents a low noise amplifier(LNA),which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm RF-CMOS *** circuit was analyzed and a new optimization method for a folded cascode LNA was *** results of the proposed circuit demonstrated a power gain of 14.13 dB,consuming 3 mW DC power,showing 1.96 dB NF and an input 1-dB compression point of -19.9 *** input power matching(S_(11)) and output power matching(S_(22)) were below -10 *** results indicate that this LNA is fully applicable to low voltage and low power applications.
This paper presents a differential low power low noise amplifier designed for the wireless sensornetwork (WSN) in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate(CG) topology has be...
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This paper presents a differential low power low noise amplifier designed for the wireless sensornetwork (WSN) in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate(CG) topology has been designed as the *** first stage is a capacitive cross-coupling *** can reduce the power and noise *** second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable *** inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A "double-π" circuit model has been built as the inductor model by iteration in *** inductor has been fabricated separately to verify the model. The LNA has been fabricated and *** LNA works well centered at 2.44 *** measured gain S_(21) is variable with high gain at 16.8 dB and low gain at 1 *** NF(noise figure) at high gain mode is 3.6 dB,the input referenced 1 dB compression point(IP1dB) is about -8 dBm and the IIP3 is 2 dBm at low gain *** LNA consumes about 1.2 mA current from 1.8 V power supply.
Since there is much larger channel delay spread, there is serious inter-symbol interference (ISI) when ultrawideband (UWB) wireless communication systems work at high data speed. The serious ISI affects the performanc...
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Since there is much larger channel delay spread, there is serious inter-symbol interference (ISI) when ultrawideband (UWB) wireless communication systems work at high data speed. The serious ISI affects the performance of UWB systems seriously. In this paper, a scheme to suppress ISI is developed for direct sequence spread-code division multiple access (DS-CDMA) UWB systems with a high data speed and an adaptive joint chip equalization Rake (AJCE-Rake) receiver is proposed. The proposed AJCE-Rake receiver spreads the number of traditional Rake receiver taps to collect multi-path component and equalize the inter-chip interference simultaneously. Then the soft output of AJCE-Rake receiver is despreaded with the user's spreading code. Finally, the decision is made to recover the transmitted symbol. The simulation results verify that ISI is suppressed effectively and the system performance is improved evidently.
There is serious inter-symbol interference (ISI) when ultra-wideband (UWB) wireless communication systems work at high data speed since there is much larger channel delay spread. The serious ISI becomes a major factor...
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Several asynchronous duty cycle MAC protocols have been proposed for low power in the wireless sensornetworks. However, these proposed MACs pay little attention on the performance degradation in many-to-one communica...
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There are strong noise components included in the reference signal and the received signal of the ultra- wideband (UWB) differential transmitted reference (DTR) autocorrelation receiver, which impact on the receiver...
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The dynamical behavior of Colpitts oscillator driven by chaotic pulse signal that is based on the bifurcation method is analyzed in this study. We present simulation results of bifurcation in the driven Colpitts syste...
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In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18m CMOS process. The proposed charge pump circuit im...
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A 7-bit 26MS/s SAR (successive approximation register) ADC is presented in this paper for the application of ZigBee receiver. Compared to the conventional method, the set-and-down method reduces the average switching ...
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A 1.8 GHz LC VCO in 1.8-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for...
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