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Asia and South Pacific Design Automation Conference

作者： Xi Zhang Haris Javaid Muhammad Shafique Jude Angelo Ambrose Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781479977932

Future on-chip manycore systems are expected to have hundreds of cores, and to be used for a number of applications to amortize their fabrication costs. In this paper, we examine how software pipelines, which are useful for streaming/multimedia applications, can be efficiently executed on a manycore system with shared memory. The goal is to balance the stages of the pipeline under workload and resource variations. This paper presents ADAPT, a method to quickly detect bottleneck stages and add cores (workers) to those bottleneck stages at run-time. Further, if there are no idle workers, then a shuffling of workers across stages is performed to improve/maintain throughput. ADAPT is implemented in a 48-core system which is built using a commercial core and tool suite. For a variety of applications, ADAPT takes less than 2 μs for one run-time adaptation, and achieves up to 2.1× the throughput of a state-of-the-art method (which is modified and implemented in the same system for a fair comparison). These results illustrate the applicability of ADAPT for fine-grained run-time management of manycore systems to achieve high throughput for software pipelines.

关键词： Pipelines Delays Software Throughput Pipeline processing Steady-state Dynamic scheduling

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Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores

Soft Error-Aware Architectural Exploration for Designing Rel...

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Design, Automation & Test in Europe Conference & Exhibition

作者： Arun Subramaniyan Semeen Rehman Muhammad Shafique Akash Kumar J?rg Henkel University of Michigan-Ann Arbor USA Chair for Processor Design TU Dresden Germany Institute of Computer Engineering Vienna University of Technology (TU Wien) Austria Chair for Embedded Systems Karlsruhe Institute of Technology Germany

ISBN: (纸本)9781509058266

Mainstream multi-core processors employ large multilevel on-chip caches making them highly susceptible to soft errors. We demonstrate that designing a reliable cache hierarchy requires understanding the vulnerability interdependencies across different cache levels. This involves vulnerability analyses depending upon the parameters of different cache levels (partition size, line size, etc.) and the corresponding cache access patterns for different applications. This paper presents a novel soft error-aware cache architectural space exploration methodology and vulnerability analysis of multi-level caches considering their vulnerability interdependencies. Our technique significantly reduces exploration time while providing reliability-efficient cache configurations. We also show applicability/benefits for ECC-protected caches under multi-bit fault scenarios.

关键词： considering vulnerability providing

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Progress in distributed operating systems and distributed systems management

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1990年

作者： Schreoder-Preikschat W. Zimmer W. Gesellschaft fur Mathematik und Datenverarbeitung. European Workshop on Progress in Distributed Operating Systems and Distributed Systems Management

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SuperNet: Multimode interconnect architecture for manycore chips

SuperNet: Multimode interconnect architecture for manycore c...

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Design Automation Conference

作者： Haseeb Bokhari Haris Javaid Muhammad Shafique Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. USA Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

Designers of the on-chip interconnect for manycore chips are faced with the dilemma of meeting performance, power and reliability requirements for different operational scenarios. In this paper, we propose a multimode on-chip interconnect called SuperNet. This interconnect can be configured to run in three different modes: energy efficient mode; performance mode; and, reliability mode. Our proposed interconnect is based on two parallel multi-vt optimized packet switched network-on-chip (NoC) meshes. We describe the circuit design techniques and architectural modifications required to realize such a multimode interconnect. Our evaluation with diverse set of applications show that the energy efficient mode can save on average 40% NoC power, whereas the performance mode can improve the core IPC by up to 13% on selected high MPKI applications. The reliability mode provides protection against soft errors in the router's data path through byte oriented SECDED codes that can correct up to 8 bit errors and detect up to 16 bit errors in a 64 bit flit, whereas the router's control path is protected through DMR lock step execution.

关键词： Frequency modulation Reliability computer architecture System-on-chip Switches Microprocessors

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Malleable NoC: Dark silicon inspired adaptable Network-on-Chip 15

Malleable NoC: Dark silicon inspired adaptable Network-on-Ch...

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Design, Automation and Test in Europe Conference and Exhibition

ISBN: (纸本)9783981537048

Network on Chip (NoC) has been envisioned as a scalable fabric for many core chips. However, NoCs can consume a considerable share of chip power. Moreover, diverse applications are executed in these multicore, where each application imposes a unique load on the NoC. To realise a NoC which is Energy and Delay efficient, we propose combining multiple VF optimized routers for each node (in traditional NoCs, we have only a single router per node) for efficient NoC for Dark Silicon chips. We present a generic NoC with routers designed for different VF levels, which are distributed across the chip. At runtime, depending on application profile, we combine these VF optimized routers to form constantly changing energy efficient NoC fabric. We call our architecture Malleable NoC. In this paper, we describe the architectural details of the proposed architecture and the runtime algorithms required to dynamically adapt the NoC resources. We show that for a variety of multi program benchmarks executing on Malleable NoC, Energy Delay product (EDP) can be reduced by up to 46% for widely differing workloads. We further show the effect on EDP savings for differing amounts of dark silicon area budget.

关键词： Switches Silicon Multicore processing System-on-chip Runtime Clocks

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Scalable Dynamic Task Scheduling on Adaptive Many-Core

Scalable Dynamic Task Scheduling on Adaptive Many-Core

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Vanchinathan Venkataramani Anuj Pathania Muhammad Shafique Tulika Mitra Jörg Henkel School of Computing National University of Singapore Singapore Institute of Computer Engineering Vienna University of Technology (TU Wien) Austria Chair of Embedded System Karlsruhe Institute of Technology Germany

ISBN: (纸本)9781538666906

Workloads from autonomous systems project an unprecedented processing demand onto their underlying embedded processors. Workload comprises of an ever-changing mix of multitudes of sequential and parallel tasks. Adaptive many-core processors with their immense yet flexible processing potential are up to the challenge. Adaptive many-core house together tens of base cores capable of forming more complex cores at run-time. Adaptive many-cores, therefore, can accelerate both sequential and parallel tasks whereas non-adaptive many-cores can only accelerate the latter. Adaptive many-cores can also reconfigure themselves to conform to the needs of any workload whereas non-adaptive many-cores - homogeneous or heterogeneous - are inherently limited given their immutable design. The accompanying qualitative schedule is the key to achieving the real potential of an adaptive many-core. The scheduler must move base cores between tasks on the fly to meet the goals of the overlying autonomous system. The scheduler also needs to scale up with the increase in the number of cores in adaptive many-cores without making compromises on the schedule quality. We present a near-optimal distributed scheduler for maximizing performance on adaptive many-cores. We also introduce an online performance prediction technique for adaptive many-cores that enable the proposed scheduler to operate without any task profiling.

关键词： Task analysis Dynamic scheduling Multicore processing Adaptation models Out of order Benchmark testing

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Formal verification of distributed dynamic thermal management 13

Formal verification of distributed dynamic thermal managemen...

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IEEE International Conference on computer-Aided Design

作者： Muhammad Ismail Osman Hasan Thomas Ebi Muhammad Shafique Jörg Henkel School of Electrical Engineering and Computer Science National University of Sciences and Technology Islamabad Pakistan Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany

ISBN: (纸本)9781479910694

Simulation is the state-of-the-art analysis technique for distributed thermal management schemes. Due to the numerous parameters involved and the distributed nature of these schemes, such non-exhaustive verification may fail to catch functional bugs in the algorithm or may report misleading performance characteristics. To overcome these limitations, we propose a methodology to perform formal verification of distributed dynamic thermal management for many-core systems. The proposed methodology is based on the SPIN model checker and the Lamport timestamps algorithm. Our methodology allows specification and verification of both functional and timing properties in a distributed many-core system. In order to illustrate the applicability and benefits of our methodology, we perform a case study on a state-of-the-art agent-based distributed thermal management scheme.

关键词： Timing Model checking System recovery Computational modeling Thermal management Analytical models Automata

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Enhancing Nanosatellite Dependability Through Autonomous Chip-Level Debug Capabilities

Enhancing Nanosatellite Dependability Through Autonomous Chi...

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ARCS 2016;29th International Conference on architecture of Computing Systems

作者： Christian M. Fuchs Nikolaus Dafinger Martin Langer Carsten Trinitis Chair of Space Systems Engineering Faculty of Aerospace Engineering Computer Engineering Laboratory Delft University of Technology Institute for Astronautics Technical University Munich Chair for Computer Architecture and Organization Technical University Munich

Modern embedded technology enables a high level of compute performance at the cost of little energy. Hence, miniaturized satellite development has begun to rely upon conventional application processor architectures an... 详细信息

关键词： satellite development nano satellites chip level Storage capacity debugger Job Performance Field programmable gate arrays embedded technology Processor architectures

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Stress-Resiliency of AI Implementations on FPGAs

Stress-Resiliency of AI Implementations on FPGAs

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International Conference on Field Programmable Logic and Applications

作者： Jonas Krautter Paul R. Genssler Gloria Sepanta Hussam Amrouch Mehdi Tahoori Institute of Computer Engineering Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Chair of Semiconductor Test and Reliability (STAR) University of Stuttgart Stuttgart Germany Chair of AI Processor Design Technical University of Munich (TUM) Munich Germany Munich Institute of Robotics and Machine Intelligence (MIRMI) Munich Germany

FPGAs have become a popular choice for machine learning acceleration for both cloud and edge devices. While traditional neural networks show impressive performance in classification tasks, Hyperdimensional Computing (HDC) is rapidly emerging as a promising novel machine learning approach for its hardware-friendly inference. In HDC, classes are embedded into high-dimensional vectors during training, and inputs can be classified by computing similarity metrics between class-vectors during inference. HDC inference is especially promoted in terms of its resiliency against errors, attributed to the large inherent redundancy. In this work, we perform a thorough experimental investigation of the fault resiliency of various FPGA-based machine learning implementations under different aspects of stress, comparing HDC with classical neural network approaches. We explore both the amount of faulty classifications as well as system crashes while subjecting the designs to timing stress using overclocking, voltage stress with excessive switching activity, and thermal stress.

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Data-driven design: Exploring new structural forms using machine learning and graphic statics

arXiv

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arXiv 2018年

作者： Fuhrimann, Lukas Moosavi, Vahid Ohlbrock, Patrick Ole D'Acunto, Pierluigi ETH Zurich Institute of Technology in Architecture Chair of Structural Design Stefano-Franscini-Platz 5 Zürich8093 Switzerland ETH Zurich ITA Chair for Computer Aided Architectural Design

The aim of this research is to introduce a novel structural design process that allows architects and engineers to extend their typical design space horizon and thereby promoting the idea of creativity in structural design. The theoretical base of this work builds on the combination of structural form-finding and state-of-the-art machine learning algorithms. In the first step of the process, Combinatorial Equilibrium Modelling (CEM) is used to generate a large variety of spatial networks in equilibrium for given input parameters. In the second step, these networks are clustered and represented in a form-map through the implementation of a Self Organizing Map (SOM) algorithm. In the third step, the solution space is interpreted with the help of a Uniform Manifold Approximation and Projection algorithm (UMAP). This allows gaining important insights in the structure of the solution space. A specific case study is used to illustrate how the infinite equilibrium states of a given topology can be defined and represented by clusters. Furthermore, three classes, related to the non-linear interaction between the input parameters and the form space, are verified and a statement about the entire manifold of the solution space of the case study is made. To conclude, this work presents an innovative approach on how the manifold of a solution space can be grasped with a minimum amount of data and how to operate within the manifold in order to increase the diversity of solutions. Copyright © 2018, The Authors. All rights reserved.

关键词： Self organizing maps

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