For the 3-D reconstruction of blood vessels skeleton from biplane angiography system, an efficient 3-D reconstruction method based on neural network(NN) is proposed in this paper. First, we find a set of 2-D correspon...
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A new restoration algorithm based on double loops and alternant iterations is proposed to restore the object image effectively from a few frames of turbulence-degraded images, Based on the double loops, the iterative ...
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A new restoration algorithm based on double loops and alternant iterations is proposed to restore the object image effectively from a few frames of turbulence-degraded images, Based on the double loops, the iterative relations for estimating the turbulent point spread function PSF and object image alternately are derived. The restoration experiments have been made on computers, showing that the proposed algorithm can obtain the optimal estimations of the object and the point spread function, with the feasibility and practicality of the proposed algorithm being convincing.
This paper proposed a novel evolutionary template-matching algorithm and studied its convergence problem. The method regarded the image matching as a global optimization problem where the main task is to find the para...
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This paper proposed a novel evolutionary template-matching algorithm and studied its convergence problem. The method regarded the image matching as a global optimization problem where the main task is to find the parameters of the affine transformation. It can greatly decrease computation amount and quickly detect the affine transformed object from noises-polluted images. Experimental results demonstrate this approach's feasibility and its potential in practical applications.
In this paper, a registration method based on Harris corners is proposed. It is composed of three steps. First, corner extraction and matching. We use the gray level information around the corner to setup the correspo...
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作者：
纪建田铮Department of Computer Science & Technology
Northwestern Polytechnical University Xi'an 710072 Department of Applied Mathematics
Northwestern Polytechnical UniversityXi'an 710072 Key Laboratory of Education Ministry for Image Processing and Intelligent ControlHuazhong University of Science & TechnologyWuhan 430074
The separation of noisy image is a very exciting area of research, especially when no prior information is available about the noisy image. In this paper, we propose a robust independent component analysis （ICA） net...
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The separation of noisy image is a very exciting area of research, especially when no prior information is available about the noisy image. In this paper, we propose a robust independent component analysis （ICA） network for separation images contaminated with high-level additive noise or outliers. We reduce the power of additive noise by adding outlier rejection rule in ICA. Extensive computer simulations confirm robustness and the excellent performance of the resulting algorithms.
Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexin...
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Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.
Efficient line-based very large scale integration architectures for the 2-D discrete wavelet transform (DWT) based on a lifting scheme, using the 9/7 wavelet filters adopted in the JPEG 2000 proposal, are proposed. Th...
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Efficient line-based very large scale integration architectures for the 2-D discrete wavelet transform (DWT) based on a lifting scheme, using the 9/7 wavelet filters adopted in the JPEG 2000 proposal, are proposed. The embedded decimation technique based on folding and time multiplexing was exploited to optimize the architecture, which reduces the size of buffer memory required and the amount of RAM access, and hence the occupied area and power consumption of the devices. Using this technique, a single-input, single-output architecture (SISOA) and a two-input, two-output architecture (TITOA) are proposed. The presented SISOA is designed to generate one output per clock cycle;the TITOA is designed to generate two outputs per clock cycle with the same memory requirement as that for SISOA, where the four sub-band coefficients of the transformed signal are available interleaved. Because only one line of data is required at a time, a single-port memory can be used. Performance analysis and comparison results demonstrate that the proposed method is economical of hardware cost and computation time. The advantages of the design also include short output latency, simple data flow, regularity, and scalability, as well as suitability for VLSI implementation. (c) 2006 Society of Photo-Optical Instrumentation Engineers.
An integrated burst-mode laser diode driver is presented for PON application. The bias current range and modulation current range are 1-75 mA and 5-80 mA respectively. The DC-coupled interface between the driver and t...
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An integrated burst-mode laser diode driver is presented for PON application. The bias current range and modulation current range are 1-75 mA and 5-80 mA respectively. The DC-coupled interface between the driver and the laser diode can tolerate the output transient voltage as low as 0.6v. The novel digital APC loop can stabilize the output average optical power and extinction ratio respectively within +/- 0.3 dBm and +/- 0.4 dB (-40 to 100 degrees C) with less than 0.6 mu s initialization time and infinite bias current and modulation current hold time. Moreover, the fast burst response is achieved with burst on/off time less than 5 ns. The chip is implemented in a TSMC 0.35-mu m SiGe BiCMOS technology and occupies an area of 1.56 x 1.67 mm(2) with power consumption of 105 mW from a supply voltage of 2.5 v.
Localization and labeling of function regions in brain is an important topic in experimental brain sciences because the huge amount of data collected by neuroscientists will become meaningless if we cannot give them a...
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ISBN:
(纸本)0819461849
Localization and labeling of function regions in brain is an important topic in experimental brain sciences because the huge amount of data collected by neuroscientists will become meaningless if we cannot give them a precise description of their locations. In this paper, we proposed a localization and labelling method of 3D MR image of rat brain based on Paxinos-Watson atlas. Our objective is to use the specific atlas to accomplish localization and labeling of specified tissue of interest (TOI) to mimic a veteran expert such that invisible or unclear anatomic function regions in the MR images of rat brain can be automatically identified and marked. We proposed a multi-step method to locate and label the TOIs from the MR image of rat brain. Firstly, preprocessing. It alms at the digitization and 3D reconstruction of the atlas and MRI of rat brain. Secondly, two-step registration. The global registration is to eliminate the big misalign and section angle offset as well as the scale between the MRI and atlas. We can choose some unambiguous and characteristic points manually, and based on these correspondences a coarse registration is obtained using affine model. The local registration is to address individual variability of rat brain that can be performed by using Snake model. Thirdly, post-processing. The goal is to locate and label the TOIs in the selected MR image of rat brain slice guided by well-registered atlas. The experiments demonstrated the feasibility of our method.
DSP/FPGA-based parallel architecture oriented to real-time imageprocessing applications is presented. The architecture is structured with high performance DSPs interconnected by FPGA. Within FPGA a FIFO interconnecti...
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