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2017 China Semiconductor Technology International Conference, CSTIC 2017

作者： Huang, Yuqian Huang, Jipan Wang, Xin'an Yang, Zhiqiang Lu, Haifang Tian, Miren Key Laboratory of Integrated Micro-System Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781509066940

In order to achieve fast IC design, reduce development cycle and cost, key lab. of integrated microsystems in Peking University proposed Array Processing for Unification Architecture(APU) which consists of four kinds of operators: computation, data path, control and MEM operators to replace the configurable logic block in current FPGA fabric. In this paper, a reconfigurable convolution operator based on APU, is presented which is used to convolutional neural network computing. The reconfigurable convolution operator is with more coarse-grain and function changeable than APU. And the process of operator synthesis is verified by simulation-based verification and formal verification separately. With the verification method proposed in this paper, certainty and completeness have been achieved. The results show that compared with the hardware design at the cost of resources based APU, this methodology can obtain hardware of suitable performance with regular structure with the cost of 34.08% less area and 25.26% lower power. © 2017 IEEE.

关键词： Neural networks

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A vision chip architecture for image recognition based on improved convolutional neural network

A vision chip architecture for image recognition based on im...

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IEEE Conference on Electron Devices and Solid-State Circuits

作者： Jijia Guo Xin'an Wang Jipan Huang Yue Tang Boyang Song Jipeng Liu Haifang Lu Zhiqiang Yang The Key Laboratory of Integrated Micro-system Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781509018314

In this paper, we propose a novel architecture of vision chip based on CNN (convolutional neural network) and improve the traditional LeNet-S algorithm. From the results of the experiment and performance, the accuracy of the proposed chip with LeNet-S increased to 97.29%. According to the characteristic of deep pipeline among independent layers of CNN, a 3-stage pipeline CCE (Convolutional Computing Element) is designed and also introduce the logical data flow in CCE array in detail. Finally the data compression and decompression circuit are added to the vision system to reduce the bandwidth of off-chip memory which is the highest cost in data transmission. The storage reduction is nearly to 30%, depending on the image processed.

关键词： Decision support systems Conferences Electron devices Solid state circuits Hafnium

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Correction to: 2021 Taxonomic update of phylum Negarnaviricota (Riboviria: Orthornavirae), including the large orders Bunyavirales and Mononegavirales

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Archives of virology 2021年第12期166卷 3567-3579页

作者： Jens H Kuhn Scott Adkins Bernard R Agwanda Rim Al Kubrusli Sergey V Alkhovsky Gaya K Amarasinghe Tatjana Avšič-Županc María A Ayllón Justin Bahl Anne Balkema-Buschmann Matthew J Ballinger Christopher F Basler Sina Bavari Martin Beer Nicolas Bejerman Andrew J Bennett Dennis A Bente Éric Bergeron Brian H Bird Carol D Blair Kim R Blasdell Dag-Ragnar Blystad Jamie Bojko Wayne B Borth Steven Bradfute Rachel Breyta Thomas Briese Paul A Brown Judith K Brown Ursula J Buchholz Michael J Buchmeier Alexander Bukreyev Felicity Burt Carmen Büttner Charles H Calisher Mengji Cao Inmaculada Casas Kartik Chandran Rémi N Charrel Qi Cheng Yuya Chiaki Marco Chiapello Il-Ryong Choi Marina Ciuffo J Christopher S Clegg Ian Crozier Elena Dal Bó Juan Carlos de la Torre Xavier de Lamballerie Rik L de Swart Humberto Debat Nolwenn M Dheilly Emiliano Di Cicco Nicholas Di Paola Francesco Di Serio Ralf G Dietzgen Michele Digiaro Olga Dolnik Michael A Drebot J Felix Drexler William G Dundon W Paul Duprex Ralf Dürrwald John M Dye Andrew J Easton Hideki Ebihara Toufic Elbeaino Koray Ergünay Hugh W Ferguson Anthony R Fooks Marco Forgia Pierre B H Formenty Jana Fránová Juliana Freitas-Astúa Jingjing Fu Stephanie Fürl Selma Gago-Zachert George Fú Gāo María Laura García Adolfo García-Sastre Aura R Garrison Thomas Gaskin Jean-Paul J Gonzalez Anthony Griffiths Tony L Goldberg Martin H Groschup Stephan Günther Roy A Hall John Hammond Tong Han Jussi Hepojoki Roger Hewson Jiang Hong Ni Hong Seiji Hongo Masayuki Horie John S Hu Tao Hu Holly R Hughes Florian Hüttner Timothy H Hyndman M Ilyas Risto Jalkanen Dàohóng Jiāng Gilda B Jonson Sandra Junglen Fujio Kadono Karia H Kaukinen Michael Kawate Boris Klempa Jonas Klingström Gary Kobinger Igor Koloniuk Hideki Kondō Eugene V Koonin Mart Krupovic Kenji Kubota Gael Kurath Lies Laenen Amy J Lambert Stanley L Langevin Benhur Lee Elliot J Lefkowitz Eric M Leroy Shaorong Li Longhui Li Jiànróng Lǐ Huazhen Liu Igor S Lukashevich Piet Maes William Marciel de Souza Marco Marklewitz Sergio H Marshall Shin-Yi L Marzano Se Integrated Research Facility at Fort Detrick National Institute of Allergy and Infectious Diseases National Institutes of Health Frederick MD USA. kuhnjens@mail.nih.gov. United States Department of Agriculture Agricultural Research Service US Horticultural Research Laboratory Fort Pierce FL USA. Zoology Department National Museums of Kenya Nairobi Kenya. Jomo Kenyatta University of Agriculture & Technology Nairobi Kenya. Division Phytomedicine Faculty of Life Sciences Humboldt-Universität zu Berlin Berlin Germany. D.I. Ivanovsky Institute of Virology of N.F. Gamaleya National Center on Epidemiology and Microbiology of Ministry of Health of Russian Federation Moscow Russia. Department of Pathology and Immunology Washington University School of Medicine St. Louis MO USA. Faculty of Medicine University of Ljubljana Ljubljana Slovenia. Centro de Biotecnología y Genómica de Plantas Universidad Politécnica de Madrid-Instituto Nacional de Investigación y Tecnología Agraria y Alimentaria Campus de Montegancedo Pozuelo de Alarcón Madrid Spain. Departamento de Biotecnología-Biología Vegetal Escuela Técnica Superior de Ingeniería Agronómica Alimentaria y de Biosistemas Universidad Politécnica de Madrid Madrid Spain. Center for Ecology of Infectious Diseases Department of Infectious Diseases Department of Epidemiology and Biostatistics Insitute of Bioinformatics University of Georgia Athens GA USA. Institute of Novel and Emerging Infectious Diseases Friedrich-Loeffler-Institut Federal Research Institute for Animal Health Greifswald-Insel Riems Germany. Department of Biological Sciences Mississippi State University Mississippi State MS USA. Center for Microbial Pathogenesis Institute for Biomedical Sciences Georgia State University Atlanta GA USA. Edge BioInnovation Consulting and Mgt Frederick MD USA. Institute of Diagnostic Virology Friedrich-Loeffler-Institut Greifswald-Insel Riems Germany. UFyMA INTA-CONICET Cordoba Argentina. Genomics and Bioinformatics D

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A high-level description method of digital IC based on dataow driven operators

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Journal of Computational Information systems 2014年第15期10卷 6347-6361页

作者： Yong, Shanshan Wang, Xin'an Xie, Zheng Guo, Zhaoyang Key Lab of Integrated Micro-system Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

In this paper we propose a high-level description method of digital IC based on a new collection of circuit components, dataow driven operators (DFDOs), to short time-to-market with fewer costs. The complex period precision control design in synchronous digital IC, which requires most of design and verification effort, is replaced by the design of dataow that exists in original algorithm and circuit system architecture according to this method which is easily and effciently implementable. The synchronization problem is solved through the synchronization logic circuit, which implements handshake protocol instead of global synchronous clock, inside of each DFDO. DFDO is classified as four kinds, which are soundness to support all digital IC design as a new collection of circuit components like standard cells, and they are computation DFDO, datapath DFDO, controller DFDO and memory DFDO. A high-level abstract language APU C which combines ANSI C and verilog to do the dataow design is also proposed which is subject to higher design effciency with less code amount and verification effort. To fully quantify this method and the performance of circuits designed by this method, a 512-point radix-2 fixed-point FFT is presented. The result shows that our work has a comparable performance on area, speed and power. © 2014 Binary Information Press

关键词： Timing circuits

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Reconfigurable operators: New configuration logic blocks for novel FPGA

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Journal of Information and Computational science 2014年第12期11卷 4153-4166页

作者： Yong, Shanshan Wang, Xin'an Xie, Zheng Cao, Ying Key Lab. of Integrated Micro-System Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

For current FPGA architectures, the fine-grain programmable blocks are the most flexible ones. However, they bring in massive configuration bits-stream and much performance loss. In this paper, we propose new configuration logic blocks for the latest FPGA, a collection of Reconfigurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the flexibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Specific integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use configuration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on configuration bits-stream and comparable delay compared with Virtex5 FPGA. © 2014 Binary Information Press

关键词： Field programmable gate arrays (FPGA)

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A novel reuse technology of extended finite state machine at the transaction level based on UVM

A novel reuse technology of extended finite state machine at...

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2014 3rd International Conference on Electrical and Electronics engineering(ICEEE 2014)

作者： Zheng Xie Xin'an Wang Zhibin Lian Shanshan Yong Key Lab of Integrated Micro System Science Engineering and Application Shenzhen Graduate School of Peking University

The reuse of verification code and methodology is a major factor providing significant acceleration of the overall verification efficiency. The verification system reusability is supported by a flexible user interface, environment structure, testbench design, and verification methodology. In this contribution, we proposed a novel reuse technology of extended finite state machine at the transaction level to simultaneously implement scenario generator, scenario coverage collector, and reference model. Associated with the Application Program Interface(API) function library based on Universal Verification Methodology(UVM), an extended finite state machine was recorded by the state machine component in Verification Expert system(VES) toolbox to generate specific code automatically. The APIs are encapsulated in the UVM library as a part of reuse resource that can reduce the amount of code greatly, provide clear architecture for functional debugging, and produce test cases automatically.

关键词： verification reuse extended finite state machine UVM

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Development of a Mind-controlled Android Racing Game using a Brain Computer Interface(BCI)

Development of a Mind-controlled Android Racing Game using a...

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2014 4th IEEE International Conference on Information science and Technology

作者： Guobin Wu Zheng Xie Xin'an Wang Key Lab of Integrated Micro System Science Engineering and Application Shenzhen Graduate School of Peking University

Brain computer interface(BCI) is to provide a direct communication or control channel between human's brain and external devices. Recently, with the development of BCI, several research institutions and organizations have developed some games that are interacted with BCI to enrich user's experience. However, most of these games are only used in computers and just focus on the realization of direction strategies. To meet the potential increasing Android smartphone users' needs and explore interacting game processes with people's mental states, this paper designs an Android 3D racing game controlled by mental states like attention and meditation. In this application, with the feedbacks of a Bluetooth BCI called Mindset, the racing car's speed and part of game scenarios can be in the charge of user's mental states.

关键词： BCI Development of a Mind-controlled Android Racing Game using a Brain Computer Interface

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Development of a mind-controlled Android racing game using a brain computer interface (BCI)

Development of a mind-controlled Android racing game using a...

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International Conference on Information science and Technology (ICIST)

作者： Guobin Wu Zheng Xie Xin'an Wang Key Lab of Integrated Micro System Science Engineering and Application Shenzhen Graduate School of Peking University Shenzhen China

Brain computer interface (BCI) is to provide a direct communication or control channel between human's brain and external devices. Recently, with the development of BCI, several research institutions and organizations have developed some games that are interacted with BCI to enrich user's experience. However, most of these games are only used in computers and just focus on the realization of direction strategies. To meet the potential increasing Android smartphone users' needs and explore interacting game processes with people's mental states, this paper designs an Android 3D racing game controlled by mental states like attention and meditation. In this application, with the feedbacks of a Bluetooth BCI called Mindset, the racing car's speed and part of game scenarios can be in the charge of user's mental states.

关键词： Games Bluetooth Androids Humanoid robots Smart phones Message systems Payloads

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A novel intelligent verification platform based on a structured analysis model

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science China(Information sciences) 2013年第6期56卷 167-180页

作者： XIE Zheng WANG XinAn LIAN ZhiBin LUO YongGui HU ZiYi Key Laboratory of Integrated Micro-system Science and Engineering Applications Peking University Shenzhen Graduate School EDA Center of Chinese Academy of Sciences

An intelligent verification platform based on a structured analysis model is *** an abstract model mechanism with specific signal interfaces for user callback,the unified structured analysis data,shared by the electronic system level design,functional verification,and performance evaluation,enables efficient management review,auto-generation of code,and modeling in the transaction *** introduce the class tree,flow parameter diagram,structured flow chart,and event-driven finite state machine as structured analysis *** a sand table to carry maps from different perspectives and levels via an engine,this highly reusable platform provides the mapping topology to search for unintended consequences and the graph theory for comprehensive coverage and smart test *** results show that the engine generates efficient test sequences,with a sharp increase in coverage for the same vector count compared with a random test.

关键词： intelligent verification platform verification automation structured analysis model mapping topology graph theory algorithm

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GALS Architecture of H.264 Video Encoding system on DN-DualV6-PCIe-4 FPGA Platform

GALS Architecture of H.264 Video Encoding System on DN-DualV...

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2012 IEEE 11th International Conference on Signal Processing(ICSP 2012)

作者： Qihua Yang Teng Wang Xindong Su Lijia Wang Xin'an Wang Key Lab of Integrated Micro-Systems Science Engineering and Applications Peking University Shenzhen Graduate School

ISBN: (纸本)9781467321969

To manage the increasing complexity of modern digital systems, Globally-Asynchronous Locally-Synchronous (GALS) is considered a promising solution, which is now widely adopted in large FPGA designs. The GALS methodology can effectively maximize the performance-power-ratio of the electronic system along with great reuse capability. With multiple clock domains in a GALS system, the accuracy with data transmission between different clock domains counts for a lot. In this paper, a GALS architecture of H.264 video encoding system is implemented on the DN-DualV6-PCIe-4 FPGA platform from the Dini Group. The data rate conversion module among different clock domains is designed with a stream controller and asynchronous FIFOs, in which gray code is applied to avoid metastability. The experiment results show the correctness and effectiveness of the proposed implementation. Furthermore, the proposed GALS scheme can be applied as a configurable architecture for more complicated applications.

关键词： GALS H.264 video encoding FPGA prototyping data rate conversion

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