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2012 3rd IEEE/IET International Conference on Audio, Language and Image Processing, ICALIP 2012

作者： Lu, Zhiyuan Shen, Ling Yuan, Yule Zhao, Yong Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781467301718

Performance of content-based image retrieval technology used in clothing image retrieval cannot meet user's requirement due to the 'semantic gap' between low-level visual features and the richness of human semantics and it's time consuming to searching images in a growing number on the internet. In order to reduce the 'semantic gap' and improve the searching speed, this paper introduces a novel clothing image retrieval method based on color semantic classification. In this method, database images are classified into different categories with color semantic features and indexed by their visual features. In the retrieval process, images with the same semantic category are selected as candidates and further ranked by their visual features. The sematic information can also be used integrated with text information labeled on the internet. Experimental results demonstrate our proposed method provides promising retrieval performance in less time than previous methods. © 2012 IEEE.

关键词： Semantics

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Theory and verification of operator design methodology

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science China(Information sciences) 2012年第2期55卷 480-490页

作者： HU ZiYi1,ZHAO Yong1,WANG XinAn1,HUANG Ru2,WANG Teng1 & ZHANG Xing2 1key lab of integrated microsystem science and engineering applications,Peking University Shenzhen Graduate School,Shenzhen 518055,China 2Institute of Microelectronics,Peking University,Beijing 100871,China 1. Key Lab of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China2. Institute of Microelectronics Peking University Beijing 100871 China

Non-recurring-engineering(NRE)and time-to-market play an increasingly important role in the field of IC ***,with the continuous development of IC manufacturing technology,it is necessary to propose a novel design methodology to shorten design cycle and enhance design *** this paper,operator design methodology(ODM)is presented and an H.264 encoder is implemented as a *** to the flow of ODM,the register transfer level(RTL)design of H.264 encoder has been accomplished with 15 man-months,which is lower than the average 19 man-months in the field of traditional application specific integrated circuit(ASIC)***,with the advantage of operator design library,the design has a comparable performance with other ASIC *** obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 30 frames per second,working at 167 MHz with SMIC 0.13 μm CMOS *** results provide good evidence for the practicability and efficiency of ODM.

关键词： operator design methodology H.264 encoder integrated circuit hardware

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GALS Architecture of H.264 Video Encoding System on DN-DualV6-PCIe-4 FPGA Platform

GALS Architecture of H.264 Video Encoding System on DN-DualV...

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2012 IEEE 11th International Conference on Signal Processing(ICSP 2012)

作者： Qihua Yang Teng Wang Xindong Su Lijia Wang Xin'an Wang Key Lab of Integrated Micro-Systems Science Engineering and Applications Peking University Shenzhen Graduate School

ISBN: (纸本)9781467321969

To manage the increasing complexity of modern digital systems, Globally-Asynchronous Locally-Synchronous (GALS) is considered a promising solution, which is now widely adopted in large FPGA designs. The GALS methodology can effectively maximize the performance-power-ratio of the electronic system along with great reuse capability. With multiple clock domains in a GALS system, the accuracy with data transmission between different clock domains counts for a lot. In this paper, a GALS architecture of H.264 video encoding system is implemented on the DN-DualV6-PCIe-4 FPGA platform from the Dini Group. The data rate conversion module among different clock domains is designed with a stream controller and asynchronous FIFOs, in which gray code is applied to avoid metastability. The experiment results show the correctness and effectiveness of the proposed implementation. Furthermore, the proposed GALS scheme can be applied as a configurable architecture for more complicated applications.

关键词： GALS H.264 video encoding FPGA prototyping data rate conversion

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System-level power estimation with on-chip bus performance monitoring units in PKU-DSPII SoC

System-level power estimation with on-chip bus performance m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Ni, Xiaoyu Wang, Teng Zhao, Yueming Su, Xindong Wang, Xin'an Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

Runtime system-level power estimation is essential for dynamic power adaptation in integrated circuits. Indirect power estimation using a CPU performance monitoring unit (PMU) is widely used in modern microprocessors for its low cost. However, the existing CPU PMUs only monitor the activities of core and cache, resulting in accuracy limitation in power estimation for systems containing heterogeneous devices. In this paper, an on-chip bus PMU (OCB PMU) is proposed for PKU-DSPII SOC to achieve accurate system-level power estimation by taking range of peripheral devices into account. By monitoring the on-chip bus signals which indicate almost all the information of the system behavior, an OCB PMU is able to recognize different types of devices. By imitating the internal behavior of every device triggered by OCB signals using an energy state machine (ESM), an OCB PMU is capable of accurate power estimation of heterogeneous devices with complicated behavior. The proposed PMUs can also flexibly adapt to different SoC architectures. © 2012 IEEE.

关键词： System-on-chip

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Syntactic representation transformation in operator design method based on ANTLR tool

Syntactic representation transformation in operator design m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Zhao, Yueming Wang, Teng Ni, Xiaoyu Wang, Xin'an Xie, Zheng Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

With the development of manufacturing technology and increasing complexity of functionality, traditional IC design method has become difficult to meet the demands of limited time-to-market and researchers' interests have been concentrated on novel design methods such as high-level synthesis, in which operator design method is one of the most promising solutions. In this paper, ANTLR tool is applied to conduct the transformation from C language to high-level operator language, which is a key step in the operator design method. The transformation procedure is comprised of four parts, namely lexical analysis, syntax analysis, AST analysis, and template emission. With a variety of experiments of different grammatical features and sentence structures of C language, the proposed syntactic representation transformation has been proven comprehensive and successful based on the proper application of ANTLR tool. Furthermore, the proposed scheme provides a good guideline for the subsequent working flow of operator design method. © 2012 IEEE.

关键词： High level synthesis

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High-level power estimation model for SOC with FPGA prototyping

High-level power estimation model for SOC with FPGA prototyp...

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4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Wang, Lijia Wang, Xin'an Wang, Teng Yang, Qihua Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781467329811

Power consumption reduction has become a first-order requirement for modern IC design, and techniques of high level power estimation are urgently in need for the sake of achieving maximal power reduction with minimal cost by optimizing the design early in the design process. This paper presents a high level power estimation model for system-on-chip (SOC) architectures on FPGA. Working with a system-level SOC synthesis framework, the proposed model takes primary power data as foundation and power estimation is conducted with regard to major event signatures such as bus and memory read/write. Besides, the anomalistic change of LUT numbers in the hardware implementation process is then taken into account, which allows more accurate and efficient power estimation providing invaluable directions for further optimization process. With the proposed model, SOC architectures are designed, and power estimation results of the model are compared with the results from real measurements on a Xilinx Virtex-5 FPGA board. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Semantic Classification Based Clothing Image Retrieval

Semantic Classification Based Clothing Image Retrieval

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International Conference on Audio, Language and Image Processing

作者： Zhiyuan Lu Ling Shen Yule Yuan Yong Zhao Key Lab of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School

ISBN: (纸本)9781467301732

关键词： image retrieval Semantics content-based image retrieval Clothing Visualization Internets User needs

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FPGA implementation and verification system of H.264/AVC encoder for HDTV applications

FPGA implementation and verification system of H.264/AVC enc...

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Computer science and Information engineering, CSIE 2012

作者： Wang, Teng Chen, Chih-Kuang Yang, Qi-Hua Wang, Xin-An Key Lab. of Integrated Microsystems Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9783642302220

For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time encoding for HDTV applications (720P@60fps) with a PSNR around 34 db. The encoder was finally implemented with SMIC 65nm CMOS technology for silicon verification. © 2012 Springer-Verlag GmbH.

关键词： Field programmable gate arrays (FPGA)

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Poster abstracts

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Sleep and Biological Rhythms 2016年第1期5卷 A1-A189页

作者： J. Ferrie M. Shipley F. Cappuccio E. Brunner M. Miller M. Kumari M. Marmot A. Coenen J. L. Castillo F. Araya G. Bustamante L. Montecino C. Torres S. Oporto J. Gronli E. Fiske R. Murison B. Bjorvatn E. Sorensen R. Ursin C. M. Portas S. Rajaraman A. Gribok N. Wesensten T. Balkin J. Reifman N. Dursunoglu S. Ozkurt S. Baser O. Delen S. Sarikaya P. Sadler P. Mitchell D. Françon M. Decobert B. Herve A. Richard G. Griebel P. Avenet B. Scatton G. L. Fur D. Eckert A. Jordan A. Wellman S. Smith A. Malhotra D. White D. Bruck I. Thomas A. Kritikos W. Oertel K. Stiasny-Kolster D. Garcia-Borreguero W. Poewe B. Hoegl R. Kohnen E. Schollmayer J. Keffel C. Trenkwalder A. Valle S. Roizenblatt F. Fregni P. Boggio S. Tufik K. Ward L. Robertson L. Palmer P. Eastwood D. Hillman J. Lee S. Mukherjee V. de Padova G. Barbato G. Ficca I. Zilli P. Salzarulo M. Veldi T. Hion V. Vasar M. Kull L. Nowak J. Davis Y. Latzer O. Tzischinsky S. Crowley M. Carskadon M. Anca-Herschkovitsch D. Frey J. Ortega C. Wiseman C. Farley K. Wright A. Campbell A. Neill K. Spiegel R. Leproult E. Tasali N. Scherberg E. van Cauter A. T. Noradina N. A. Karim I. Norlinah A. A. Raymond R. Sahathevan B. Hamidon E. Werth R. Poryazova R. Khatami C. Bassetti R. G. Beran L. Ainley G. Holand J. Duncan H. Kinney B. Davis B. Hood S. Frey C. Schmidt M. Hofstetter P. Peigneux C. Cajochen W.-P. Hu J.-D. Li C. Zhang L. Boehmer J. Siegel Q.-Y. Zhou Y. Sagawa H. Kondo T. Takemura H. Kanayama Y. Kaneko M. Sato T. Kanbayashi Y. Hishikawa T. Shimizu A. Viola L. James L. Schlangen D.-J. Dijk R. Andretic Y.-C. Kim K.-A. Han F. Jones R. Greenspan L. Sanford L. Yang X. Tang K. Dieter E. Uta H. Sven M. Richard N. Oyane S. Pallesen F. Holsten Y. Inoue M. Fujita N. Emura K. Kuroda N. Uchimura A. Johnston J. Astbury G. Kennedy K. Hoedlmoser M. Schabus T. Pecherstorfer S. Moser G. Gruber P. Anderer W. Klimesch N. Naidoo M. Ferber A. Pack D. Neu O. Mairesse G. Hoffmann A. Dris L. Lambrecht P. Linkowski P. Verbanck O. Le Bon N. Matsuura M. Yamao N. Adachi R. Aritomi Y. Komada H. Tanaka S. Shirak University College London London UK University College London London USA Warwick Medical School London UK Warwick Medical School Coventry USA Radboud University Nijmegen Nijmegen Netherlands Department of Neurology University of Chile Santiago Chile Neurology Service Hospital del Salvador Santiago Chile Family Health Center Juan Pablo II Santiago Chile Department of Biomedicine Section on Physiology Univeristy of Bergen Bergen Norway Department of Public Health and Primary Health Care Univeristy of Bergen Bergen Norway Department of Public Health and Primary Health Care University of Bergen Bergen Norway Norwegian Competence Center for Sleep Disorders Haukeland University Hospital Bergen Norway Department of Child and Adolescent Psychiatry Haukeland University Hospital Univeristy of Bergen Bergen Norway Department of Biomedicine University of Bergen Bergen Norway US Army Medical Research and Materiel Command Fort Detrick Frederick USA Walter Reed Army Institute of Research Silver Spring USA Department of Behavioral Biology Walter Reed Army Institute of Research Silver Spring USA Faculty Department of Pulmonology Pamukkale University Medical Denizli Turkey University of Ballarat Ballarat Australia Sanofi-Aventis Recherche et Developpement Paris France Brigham and Women’s Hospital Harvard Medical School Boston USA The University of Queensland Adelaide Australia School of Psychology University of Queensland Brisbane Australia The University of Queensland Brisbane Australia Victoria University Melbourne Australia Department of Psychology Victoria University Melbourne Australia School of Psychology Victoria University Melbourne Australia Philips-Universität Marburg Germany Philips-Universitaet-Marburg Marburg Germany Instituto de Investigaciones del Sueno Madrid Spain Universitätsklinik für Neurologie Innsbruck Austria Universitaetsklinik fuer Neurologie Innsbruck Austria IMEREM GmbH Nuernberg Germany Schwarz Pharma AG Monheim Germany

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Study and analysis of coefficient mismatch in a MASH21 sigma—delta modulator

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Journal of Semiconductors 2010年第1期31卷 79-82页

作者：葛彬杰王新安张兴冯晓星汪清勤 Key Laboratory of Integrated Microsystem Science & Engineering Applications Shenzhen Graduate School of Peking University

The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 μm mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.

关键词： mismatch leakage modeling sigma-delta modeling DC gain

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