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Sigma-delta modulator modeling analysis and design

Journal of Semiconductors 2010年第9期31卷 79-83页

作者：葛彬杰王新安张兴冯晓星汪清勤 Key Laboratory of Integrated Microsystem Science & Engineering Applications Shenzhen Graduate School of Peking University

This paper introduces a new method for SC sigma-delta modulator *** studies the integrator＇s different equivalent circuits in the integrating and sampling *** model uses the OP-AMP input pair＇s tail current（I_0） and overdrive voltage（v_（on）） as *** modulator＇s static and dynamic errors are analyzed.A group of optimized I0 and von for maximum SNR and power x area ratio can be obtained through this *** examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively,which verifies the modeling and design criteria.

关键词： sigma-delta modeling transient behavior optimization

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Design and implementation of a novel programmable power monitor chip

Design and implementation of a novel programmable power moni...

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2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010

作者： Ge, Binjie Wang, Xin'an Zhang, Xing Feng, Xiaoxing Wang, Qingqin Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781424467372

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.

关键词： Signal processing

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Operator design methodology and implementation for H.264 entropy encoder

Operator design methodology and implementation for H.264 ent...

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International Conference on Information engineering and Computer science

作者： Hu, Ziyi Chen, Kuilin Wang, Xin'an Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9781424479412

Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to logic gate level, the size of standard cells in digital circuits is increasing correspondingly. New methodology should be proposed to meet the need for shorter time-to-market IC industry, and the requirement of advanced IC manufacturing technology. This paper proposed the concept and principle of operator design methodology, then focused on the entropy coding application by the reconfigurable operator and finally gave the synthesis data. The results show that compared with the hardware design at the same cost of resources, this methodology can obtain hardware of suitable performance with regular structure. What is more, it can improve the design speed efficiently. ©2010 IEEE.

关键词： Entropy

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Operator Design Methodology and Implementation for H.264 Entropy Encoder

Operator Design Methodology and Implementation for H.264 Ent...

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International Conference on Information engineering and Computer science (ICIECS)

作者： Ziyi Hu Kuilin Chen Xin'an Wang Key Laboratory of Integrated Microsystem Science & Engineering Applications Peking University Shenzhen China

关键词： Entropy coding Hardware Clocks Application specific integrated circuits Design methodology

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Design and implementation of a novel programmable power monitor chip

Design and implementation of a novel programmable power moni...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Binjie Ge Xin'an Wang Xing Zhang Xiaoxing Feng Qingqin Wang Key Laboratory of Integrated Microsystem Science & Engineering Applications Peking University Shenzhen China

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5 v to 5.0 v with 0.1 v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5 μm mixed signal process, the die area is 0.24mm 2 , and the quiescent current is only 3 uA.

关键词： Monitoring Pins Switches Clocks Hysteresis Capacitors Low voltage

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On Web Page extraction based on position of DIV

On Web Page extraction based on position of DIV

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International Conference on Computer and Automation engineering, ICCAE

作者： Xunhua Liu Hui Li Dan Wu Jiaqing Huang Wei Wang Li Yu Ye Wu Hengjun Xie Key Laboratory of Integrated Microsystem Science and Engineering Applications Shenzhen Graduate School Peking University Shanghai China Key Laboratory of Integrated Microsystem Science and Engineering Applications Shenzhen Graduate School of Peking University 518055 China Department of Electronics & Information Engineering Huazhong University of Science and Technology Wuhan China Value-added Service Center China Telecom Shenzhen Branch Company Limited Shenzhen China

ISBN: (纸本)9781424455850

For the popular DIV page layout in Web Pages, this paper presents a method based on the position of DIV to extract main text from the body of Web pages by reconstructing, remaining atomic DIV and analyzing DIV position. Experiments showed that the accuracy rate of extraction can reach more than 90%, with a high versatility and accuracy.

关键词： Web pages Data mining HTML Information analysis Information retrieval Containers Standards publication Cascading style sheets Microelectronics Telecommunications

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Algorithm of variable transition bandwidth FIR filters with weighted-least-square method

Algorithm of variable transition bandwidth FIR filters with ...

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2010 2nd International Conference on Computer engineering and Technology, ICCET 2010

作者： Ma, Zilong Li, Hui An, Huiyao Wang, Wei Quan, Jinguo Key Lab. of Integrated Microsystem Science and Eng. Shenzhen Graduate School PEKING University Shenzhen 518055 China Dept. of Electronics and Info. Eng. Huazhong University of Science and Technology Wuhan 430074 China Division of Information Engineering Shenzhen Graduate School Tsinghua University Shenzhen 518055 China

ISBN: (纸本)9781424463503

This paper deals with the design of variable bandwidth linear-phase FIR digital filters by weighted least square method. This proposed algorithm is constructed by a linear combination of fixed-coefficient linear-phase filters, of which the variable bandwidth characteristics are provided by an embedded tuning parameter. Using the weighted least square objective function, the optimal solution is obtained by solving a set of linear equation, which is an error function reflecting the difference between the desired variable bandwidth filter and the practical filter. The proposed algorithm can implement the variable digital filter efficiently by the familiar Farrow structure with only one variable spectral parameter that determines the bandwidth. Mathematics deduction and simulations show this algorithm is simple and effective in designing FIR variable digital filter with better performance than previous ones. © 2010 IEEE.

关键词： FIR filters

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Dynamic Context Management for Coarse-grained Reconfigurable Array DSP Architecture

Dynamic Context Management for Coarse-grained Reconfigurable...

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IEEE 8th International Conference on ASIC

作者： Liu, Yanliang Dai, Peng Wang, Xin'an Zhang, Xing Wei, Lai Zhou, Yan Sun, Yachun Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China

ISBN: (纸本)9781424438686

This paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. The technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. The proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18um CMOS process mainly for multi-media applications(1).

关键词： Coarse-grained Reconfigurable Array DSP Architecture Context switch Context reuse Runtime reconfiguration (RTR) Partially Reconfiguration

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Implementation of high-speed verification platform based on emulator for ReDSP and ReMAP

Implementation of high-speed verification platform based on ...

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2009 8th IEEE International Conference on ASIC, ASICON 2009

作者： Huang, Wei Wang, Xinan Dai, Peng Guo, Zheng Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China Mentor Graphics Corporation China

ISBN: (纸本)9781424438686

Verification of processors with high performance is becoming more and more time-consuming and even gradually turning into the bottleneck of the processor design. The Verification of Reconfiguralbe Multimedia Array Processor(ReMAP) we designed for multimedia processing and its internal component Reconfigurable DSP(ReDSP) is also no exception. A high-speed verification platform based on emulator is proposed for ReDSP and ReMAP. We demonstrate the hardware architecture of the platform and different verification modes it supports. A software verification model is proposed, and the evaluation results show a great acceleration rate compared to software simulation1. ©2009 IEEE.

关键词： Verification

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A novel PAPR reduction technique by sampling partial transmit sequences

A novel PAPR reduction technique by sampling partial transmi...

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5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009

作者： Yuzhong, Jiao Xin'an, Wang Ying, Xu Xuejiao, Liu Xuewen, Ni Key Lab. of Integrated Microsystem Science and Engineering Applications A406 Shenzhen Graduate School of Peking University Xili Shenzhen 518055 China

ISBN: (纸本)9781424436934

Optimum partial transmit sequence method (OPTS), as one of the highest-performance PAPR reduction techniques, has very high computational complexity. Most sub-optimal schemes which are based on iterative PTS (IPTS), aim at balancing PAPR reduction performance and complexity by expanding the searching space of phase factor sequence with more iterative operations. A novel scheme is presented to further lower the complexity of PTS. This scheme samples every partial transmit sequence, obtains some peak-position samples with the largest magnitudes and then constructs PTS sampling sequence. A proper phase factor sequence can be got through processing PTS sampling sequences according to the principle of OPTS or sub-optimal PTS. Because PTS sampling sequences have fewer samples, the new method can achieve a low complexity. Besides, simulation results show that the new scheme has good PAPR reduction performance. ©2009 IEEE.

关键词： Orthogonal frequency division multiplexing

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