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A novel intelligent verification platform based on a structured analysis model

science China(Information sciences) 2013年第6期56卷 167-180页

作者： XIE Zheng WANG XinAn LIAN ZhiBin LUO YongGui HU ZiYi Key Laboratory of Integrated Micro-system Science and Engineering Applications Peking University Shenzhen Graduate School EDA Center of Chinese Academy of Sciences

An intelligent verification platform based on a structured analysis model is *** an abstract model mechanism with specific signal interfaces for user callback,the unified structured analysis data,shared by the electronic system level design,functional verification,and performance evaluation,enables efficient management review,auto-generation of code,and modeling in the transaction *** introduce the class tree,flow parameter diagram,structured flow chart,and event-driven finite state machine as structured analysis *** a sand table to carry maps from different perspectives and levels via an engine,this highly reusable platform provides the mapping topology to search for unintended consequences and the graph theory for comprehensive coverage and smart test *** results show that the engine generates efficient test sequences,with a sharp increase in coverage for the same vector count compared with a random test.

关键词： intelligent verification platform verification automation structured analysis model mapping topology graph theory algorithm

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CS/Gel/MWCNTs Conductive Scaffolds Assisted by Electrical Stimulus for Skin Tissue engineering

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Biotechnology and Bioengineering 2025年 2025 May 15页

作者： Liu, Zixian Ma, Zijun Li, Nini Zhang, Jinyao Li, Meng Han, Lu Cheng, Rong Shen, Zhizhong Han, Dan Sang, Shengbo Shanxi Key Laboratory of Artificial Intelligence & Micro Nano Sensors College of Integrated Circuits Taiyuan University of Technology Shanxi Province Taiyuan China Key Lab of Advanced Transducers and Intelligent Control System of the Ministry of Education Taiyuan University of Technology Shanxi Province Taiyuan China College of chemistry and chemical Engineering North University of china Shanxi Province Taiyuan China Shanxi Research Institute of 6D Artificial Intelligence Biomedical Science Shanxi Province Taiyuan China

Hydrogel scaffolds show high potential in tissue engineering due to excellent mechanical properties and biocompatibility. However, an inherent lack of conductivity limits its application in areas requiring electrical stimulation. To address this issue, chitosan (CS)/gelatin (Gel) scaffolds were prepared with various concentrations of multi-walled carbon nanotubes (MWCNTs). Results indicated that MWCNT incorporation significantly improved both the electrical conductivity and mechanical strength of the scaffolds, with the CS/Gel/0.3% MWCNTs scaffold demonstrating superior biocompatibility compared to other formulations. Additionally, fibroblasts seeded onto the scaffolds responded positively to electrical stimulation, showing increased proliferation and elevated expression of type I and type III collagen. These findings highlight the potential of CS/Gel/MWCNTs scaffolds to enhance wound healing in skin tissue engineering. © 2025 Wiley Periodicals LLC.

关键词： Fiber bonding

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GALS Architecture of H.264 Video Encoding system on DN-DualV6-PCIe-4 FPGA Platform

GALS Architecture of H.264 Video Encoding System on DN-DualV...

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2012 IEEE 11th International Conference on Signal Processing(ICSP 2012)

作者： Qihua Yang Teng Wang Xindong Su Lijia Wang Xin'an Wang Key Lab of Integrated Micro-Systems Science Engineering and Applications Peking University Shenzhen Graduate School

ISBN: (纸本)9781467321969

To manage the increasing complexity of modern digital systems, Globally-Asynchronous Locally-Synchronous (GALS) is considered a promising solution, which is now widely adopted in large FPGA designs. The GALS methodology can effectively maximize the performance-power-ratio of the electronic system along with great reuse capability. With multiple clock domains in a GALS system, the accuracy with data transmission between different clock domains counts for a lot. In this paper, a GALS architecture of H.264 video encoding system is implemented on the DN-DualV6-PCIe-4 FPGA platform from the Dini Group. The data rate conversion module among different clock domains is designed with a stream controller and asynchronous FIFOs, in which gray code is applied to avoid metastability. The experiment results show the correctness and effectiveness of the proposed implementation. Furthermore, the proposed GALS scheme can be applied as a configurable architecture for more complicated applications.

关键词： GALS H.264 video encoding FPGA prototyping data rate conversion

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The design and implementation of a reconfigurable convolution operator based on APU

The design and implementation of a reconfigurable convolutio...

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2017 China Semiconductor Technology International Conference, CSTIC 2017

作者： Huang, Yuqian Huang, Jipan Wang, Xin'an Yang, Zhiqiang Lu, Haifang Tian, Miren Key Laboratory of Integrated Micro-System Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781509066940

In order to achieve fast IC design, reduce development cycle and cost, key lab. of integrated microsystems in Peking University proposed Array Processing for Unification Architecture(APU) which consists of four kinds of operators: computation, data path, control and MEM operators to replace the configurable logic block in current FPGA fabric. In this paper, a reconfigurable convolution operator based on APU, is presented which is used to convolutional neural network computing. The reconfigurable convolution operator is with more coarse-grain and function changeable than APU. And the process of operator synthesis is verified by simulation-based verification and formal verification separately. With the verification method proposed in this paper, certainty and completeness have been achieved. The results show that compared with the hardware design at the cost of resources based APU, this methodology can obtain hardware of suitable performance with regular structure with the cost of 34.08% less area and 25.26% lower power. © 2017 IEEE.

关键词： Neural networks

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Dynamic Context Management for Coarse-grained Reconfigurable Array DSP Architecture

Dynamic Context Management for Coarse-grained Reconfigurable...

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IEEE 8th International Conference on ASIC

作者： Liu, Yanliang Dai, Peng Wang, Xin'an Zhang, Xing Wei, Lai Zhou, Yan Sun, Yachun Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China

ISBN: (纸本)9781424438686

This paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. The technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. The proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18um CMOS process mainly for multi-media applications(1).

关键词： Coarse-grained Reconfigurable Array DSP Architecture Context switch Context reuse Runtime reconfiguration (RTR) Partially Reconfiguration

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Semantic classification based clothing image retrieval

Semantic classification based clothing image retrieval

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2012 3rd IEEE/IET International Conference on Audio, Language and Image Processing, ICALIP 2012

作者： Lu, Zhiyuan Shen, Ling Yuan, Yule Zhao, Yong Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781467301718

Performance of content-based image retrieval technology used in clothing image retrieval cannot meet user's requirement due to the 'semantic gap' between low-level visual features and the richness of human semantics and it's time consuming to searching images in a growing number on the internet. In order to reduce the 'semantic gap' and improve the searching speed, this paper introduces a novel clothing image retrieval method based on color semantic classification. In this method, database images are classified into different categories with color semantic features and indexed by their visual features. In the retrieval process, images with the same semantic category are selected as candidates and further ranked by their visual features. The sematic information can also be used integrated with text information lab.led on the internet. Experimental results demonstrate our proposed method provides promising retrieval performance in less time than previous methods. © 2012 IEEE.

关键词： Semantics

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Design and implementation of a novel programmable power monitor chip

Design and implementation of a novel programmable power moni...

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2nd Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Ge, Binjie Wang, Xin'an Zhang, Xing Feng, Xiaoxing Wang, Qingqin Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781424467372

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.

关键词： Signal processing

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system-level power estimation with on-chip bus performance monitoring units in PKU-DSPII SoC

System-level power estimation with on-chip bus performance m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Ni, Xiaoyu Wang, Teng Zhao, Yueming Su, Xindong Wang, Xin'an Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

Runtime system-level power estimation is essential for dynamic power adaptation in integrated circuits. Indirect power estimation using a CPU performance monitoring unit (PMU) is widely used in modern microprocessors for its low cost. However, the existing CPU PMUs only monitor the activities of core and cache, resulting in accuracy limitation in power estimation for systems containing heterogeneous devices. In this paper, an on-chip bus PMU (OCB PMU) is proposed for PKU-DSPII SOC to achieve accurate system-level power estimation by taking range of peripheral devices into account. By monitoring the on-chip bus signals which indicate almost all the information of the system behavior, an OCB PMU is able to recognize different types of devices. By imitating the internal behavior of every device triggered by OCB signals using an energy state machine (ESM), an OCB PMU is capable of accurate power estimation of heterogeneous devices with complicated behavior. The proposed PMUs can also flexibly adapt to different SoC architectures. © 2012 IEEE.

关键词： system-on-chip

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High-level power estimation model for SOC with FPGA prototyping

High-level power estimation model for SOC with FPGA prototyp...

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4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Wang, Lijia Wang, Xin'an Wang, Teng Yang, Qihua Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781467329811

Power consumption reduction has become a first-order requirement for modern IC design, and techniques of high level power estimation are urgently in need for the sake of achieving maximal power reduction with minimal cost by optimizing the design early in the design process. This paper presents a high level power estimation model for system-on-chip (SOC) architectures on FPGA. Working with a system-level SOC synthesis framework, the proposed model takes primary power data as foundation and power estimation is conducted with regard to major event signatures such as bus and memory read/write. Besides, the anomalistic change of LUT numbers in the hardware implementation process is then taken into account, which allows more accurate and efficient power estimation providing invaluable directions for further optimization process. With the proposed model, SOC architectures are designed, and power estimation results of the model are compared with the results from real measurements on a Xilinx Virtex-5 FPGA board. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Syntactic representation transformation in operator design method based on ANTLR tool

Syntactic representation transformation in operator design m...

引用

2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Zhao, Yueming Wang, Teng Ni, Xiaoyu Wang, Xin'an Xie, Zheng Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

With the development of manufacturing technology and increasing complexity of functionality, traditional IC design method has become difficult to meet the demands of limited time-to-market and researchers' interests have been concentrated on novel design methods such as high-level synthesis, in which operator design method is one of the most promising solutions. In this paper, ANTLR tool is applied to conduct the transformation from C language to high-level operator language, which is a key step in the operator design method. The transformation procedure is comprised of four parts, namely lexical analysis, syntax analysis, AST analysis, and template emission. With a variety of experiments of different grammatical features and sentence structures of C language, the proposed syntactic representation transformation has been proven comprehensive and successful based on the proper application of ANTLR tool. Furthermore, the proposed scheme provides a good guideline for the subsequent working flow of operator design method. © 2012 IEEE.

关键词： High level synthesis

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