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IEEE 8th International Conference on ASIC

作者： Liu, Yanliang Dai, Peng Wang, Xin'an Zhang, Xing Wei, Lai Zhou, Yan Sun, Yachun Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China

ISBN: (纸本)9781424438686

This paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. The technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. The proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18um CMOS process mainly for multi-media applications(1).

关键词： Coarse-grained Reconfigurable Array DSP Architecture Context switch Context reuse Runtime reconfiguration (RTR) Partially Reconfiguration

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Semantic classification based clothing image retrieval

Semantic classification based clothing image retrieval

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2012 3rd IEEE/IET International Conference on Audio, Language and Image Processing, ICALIP 2012

作者： Lu, Zhiyuan Shen, Ling Yuan, Yule Zhao, Yong Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781467301718

Performance of content-based image retrieval technology used in clothing image retrieval cannot meet user's requirement due to the 'semantic gap' between low-level visual features and the richness of human semantics and it's time consuming to searching images in a growing number on the internet. In order to reduce the 'semantic gap' and improve the searching speed, this paper introduces a novel clothing image retrieval method based on color semantic classification. In this method, database images are classified into different categories with color semantic features and indexed by their visual features. In the retrieval process, images with the same semantic category are selected as candidates and further ranked by their visual features. The sematic information can also be used integrated with text information lab.led on the internet. Experimental results demonstrate our proposed method provides promising retrieval performance in less time than previous methods. © 2012 IEEE.

关键词： Semantics

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Design and implementation of a novel programmable power monitor chip

Design and implementation of a novel programmable power moni...

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2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010

作者： Ge, Binjie Wang, Xin'an Zhang, Xing Feng, Xiaoxing Wang, Qingqin Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781424467372

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.

关键词： Signal processing

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ML estimation of non-virtual sub-carriers OFDM carrier frequency offset

ML estimation of non-virtual sub-carriers OFDM carrier frequ...

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Mobile Computing and Wireless Communications International Conference, MCWC 2006

作者： Bo, Hong Xin'an, Wang Gaofa, Xiao Key Lab. of Integrated Microsystem Science and Engineering Applications PKU Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9957486004

In OFDM system, because of sensitivity to carrier frequency offset, frequency offset must be compensated before DFT in the receiver. In this paper, we present a maximum likelihood estimation for carrier frequency offset, based on OFDM symbol has no virtual sub-carriers. The estimation are compose of two parts, blind estimation makes use of cyclic prefix for every symbol and data-aid estimation makes use of two consequent OFDM symbols which are similar or relative to each other. Data-aid estimation performs well and simulation result converges upon Cramer-Rao lower bound. Blind estimation performs inferior, but it can be used in tracking mode.

关键词： Orthogonal frequency division multiplexing

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Operator design methodology and implementation for H.264 entropy encoder

Operator design methodology and implementation for H.264 ent...

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International Conference on Information engineering and Computer science

作者： Hu, Ziyi Chen, Kuilin Wang, Xin'an Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9781424479412

Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to logic gate level, the size of standard cells in digital circuits is increasing correspondingly. New methodology should be proposed to meet the need for shorter time-to-market IC industry, and the requirement of advanced IC manufacturing technology. This paper proposed the concept and principle of operator design methodology, then focused on the entropy coding application by the reconfigurable operator and finally gave the synthesis data. The results show that compared with the hardware design at the same cost of resources, this methodology can obtain hardware of suitable performance with regular structure. What is more, it can improve the design speed efficiently. ©2010 IEEE.

关键词： Entropy

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Implementation of high-speed verification platform based on emulator for ReDSP and ReMAP

Implementation of high-speed verification platform based on ...

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2009 8th IEEE International Conference on ASIC, ASICON 2009

作者： Huang, Wei Wang, Xinan Dai, Peng Guo, Zheng Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China Mentor Graphics Corporation China

ISBN: (纸本)9781424438686

Verification of processors with high performance is becoming more and more time-consuming and even gradually turning into the bottleneck of the processor design. The Verification of Reconfiguralbe Multimedia Array Processor(ReMAP) we designed for multimedia processing and its internal component Reconfigurable DSP(ReDSP) is also no exception. A high-speed verification platform based on emulator is proposed for ReDSP and ReMAP. We demonstrate the hardware architecture of the platform and different verification modes it supports. A software verification model is proposed, and the evaluation results show a great acceleration rate compared to software simulation1. ©2009 IEEE.

关键词： Verification

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A novel PAPR reduction technique by sampling partial transmit sequences

A novel PAPR reduction technique by sampling partial transmi...

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5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009

作者： Yuzhong, Jiao Xin'an, Wang Ying, Xu Xuejiao, Liu Xuewen, Ni Key Lab. of Integrated Microsystem Science and Engineering Applications A406 Shenzhen Graduate School of Peking University Xili Shenzhen 518055 China

ISBN: (纸本)9781424436934

Optimum partial transmit sequence method (OPTS), as one of the highest-performance PAPR reduction techniques, has very high computational complexity. Most sub-optimal schemes which are based on iterative PTS (IPTS), aim at balancing PAPR reduction performance and complexity by expanding the searching space of phase factor sequence with more iterative operations. A novel scheme is presented to further lower the complexity of PTS. This scheme samples every partial transmit sequence, obtains some peak-position samples with the largest magnitudes and then constructs PTS sampling sequence. A proper phase factor sequence can be got through processing PTS sampling sequences according to the principle of OPTS or sub-optimal PTS. Because PTS sampling sequences have fewer samples, the new method can achieve a low complexity. Besides, simulation results show that the new scheme has good PAPR reduction performance. ©2009 IEEE.

关键词： Orthogonal frequency division multiplexing

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Theory and verification of operator design methodology

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science China(Information sciences) 2012年第2期55卷 480-490页

作者： HU ZiYi1,ZHAO Yong1,WANG XinAn1,HUANG Ru2,WANG Teng1 & ZHANG Xing2 1key lab.of integrated microsystem science and engineering applications,Peking University Shenzhen Graduate School,Shenzhen 518055,China 2Institute of Microelectronics,Peking University,Beijing 100871,China 1. Key Lab of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China2. Institute of Microelectronics Peking University Beijing 100871 China

Non-recurring-engineering(NRE)and time-to-market play an increasingly important role in the field of IC ***,with the continuous development of IC manufacturing technology,it is necessary to propose a novel design methodology to shorten design cycle and enhance design *** this paper,operator design methodology(ODM)is presented and an H.264 encoder is implemented as a *** to the flow of ODM,the register transfer level(RTL)design of H.264 encoder has been accomplished with 15 man-months,which is lower than the average 19 man-months in the field of traditional application specific integrated circuit(ASIC)***,with the advantage of operator design library,the design has a comparable performance with other ASIC *** obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 30 frames per second,working at 167 MHz with SMIC 0.13 μm CMOS *** results provide good evidence for the practicability and efficiency of ODM.

关键词： operator design methodology H.264 encoder integrated circuit hardware

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System-level power estimation with on-chip bus performance monitoring units in PKU-DSPII SoC

System-level power estimation with on-chip bus performance m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Ni, Xiaoyu Wang, Teng Zhao, Yueming Su, Xindong Wang, Xin'an Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

Runtime system-level power estimation is essential for dynamic power adaptation in integrated circuits. Indirect power estimation using a CPU performance monitoring unit (PMU) is widely used in modern microprocessors for its low cost. However, the existing CPU PMUs only monitor the activities of core and cache, resulting in accuracy limitation in power estimation for systems containing heterogeneous devices. In this paper, an on-chip bus PMU (OCB PMU) is proposed for PKU-DSPII SOC to achieve accurate system-level power estimation by taking range of peripheral devices into account. By monitoring the on-chip bus signals which indicate almost all the information of the system behavior, an OCB PMU is able to recognize different types of devices. By imitating the internal behavior of every device triggered by OCB signals using an energy state machine (ESM), an OCB PMU is capable of accurate power estimation of heterogeneous devices with complicated behavior. The proposed PMUs can also flexibly adapt to different SoC architectures. © 2012 IEEE.

关键词： System-on-chip

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High-level power estimation model for SOC with FPGA prototyping

High-level power estimation model for SOC with FPGA prototyp...

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4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Wang, Lijia Wang, Xin'an Wang, Teng Yang, Qihua Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781467329811

Power consumption reduction has become a first-order requirement for modern IC design, and techniques of high level power estimation are urgently in need for the sake of achieving maximal power reduction with minimal cost by optimizing the design early in the design process. This paper presents a high level power estimation model for system-on-chip (SOC) architectures on FPGA. Working with a system-level SOC synthesis framework, the proposed model takes primary power data as foundation and power estimation is conducted with regard to major event signatures such as bus and memory read/write. Besides, the anomalistic change of LUT numbers in the hardware implementation process is then taken into account, which allows more accurate and efficient power estimation providing invaluable directions for further optimization process. With the proposed model, SOC architectures are designed, and power estimation results of the model are compared with the results from real measurements on a Xilinx Virtex-5 FPGA board. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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