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A multi-objective optimal water strategy using time series analysis and improved genetic algorithm

Journal of Information and Computational science 2015年第6期12卷 2229-2239页

作者： Lai, Changqing Xu, Zhengchao Jiang, Yuning School of Economics and Management Tsinghua University Beijing China Wuhan National Laboratory for Optoelectronics Huazhong University of Science and Technology Wuhan China Key Lab. of Integrated Microsystem Science & Engineering Applications Shenzhen Graduate School Peking University Beijing China

Time series analysis and genetic algorithm have a good application in many fields. In present paper, we utilized graph theory, and established a multi-objective optimal water distribution model according to current situation in China. Then, we utilized time series analysis to predict water supply and demand situation, and put forward an improved genetic algorithm solution for optimal water resources strategy. Furthermore, sensitivity and effectivity of the improved genetic algorithm is fit to resolve the model. This method can be extended to other various resources-distribution fields. Copyright © 2015 Binary Information Press.

关键词： Graph theory

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Reconfigurable operators: New configuration logic blocks for novel FPGA

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Journal of Information and Computational science 2014年第12期11卷 4153-4166页

作者： Yong, Shanshan Wang, Xin'an Xie, Zheng Cao, Ying Key Lab. of Integrated Micro-System Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

For current FPGA architectures, the fine-grain programmable blocks are the most flexible ones. However, they bring in massive configuration bits-stream and much performance loss. In this paper, we propose new configuration logic blocks for the latest FPGA, a collection of Reconfigurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the flexibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Specific integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use configuration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on configuration bits-stream and comparable delay compared with Virtex5 FPGA. © 2014 Binary Information Press

关键词： Field programmable gate arrays (FPGA)

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High-level power estimation model for SOC with FPGA prototyping

High-level power estimation model for SOC with FPGA prototyp...

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4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Wang, Lijia Wang, Xin'an Wang, Teng Yang, Qihua Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781467329811

Power consumption reduction has become a first-order requirement for modern IC design, and techniques of high level power estimation are urgently in need for the sake of achieving maximal power reduction with minimal cost by optimizing the design early in the design process. This paper presents a high level power estimation model for system-on-chip (SOC) architectures on FPGA. Working with a system-level SOC synthesis framework, the proposed model takes primary power data as foundation and power estimation is conducted with regard to major event signatures such as bus and memory read/write. Besides, the anomalistic change of LUT numbers in the hardware implementation process is then taken into account, which allows more accurate and efficient power estimation providing invaluable directions for further optimization process. With the proposed model, SOC architectures are designed, and power estimation results of the model are compared with the results from real measurements on a Xilinx Virtex-5 FPGA board. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Syntactic representation transformation in operator design method based on ANTLR tool

Syntactic representation transformation in operator design m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Zhao, Yueming Wang, Teng Ni, Xiaoyu Wang, Xin'an Xie, Zheng Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

With the development of manufacturing technology and increasing complexity of functionality, traditional IC design method has become difficult to meet the demands of limited time-to-market and researchers' interests have been concentrated on novel design methods such as high-level synthesis, in which operator design method is one of the most promising solutions. In this paper, ANTLR tool is applied to conduct the transformation from C language to high-level operator language, which is a key step in the operator design method. The transformation procedure is comprised of four parts, namely lexical analysis, syntax analysis, AST analysis, and template emission. With a variety of experiments of different grammatical features and sentence structures of C language, the proposed syntactic representation transformation has been proven comprehensive and successful based on the proper application of ANTLR tool. Furthermore, the proposed scheme provides a good guideline for the subsequent working flow of operator design method. © 2012 IEEE.

关键词： High level synthesis

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System-level power estimation with on-chip bus performance monitoring units in PKU-DSPII SoC

System-level power estimation with on-chip bus performance m...

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2012 IEEE 12th International Conference on Computer and Information Technology, CIT 2012

作者： Ni, Xiaoyu Wang, Teng Zhao, Yueming Su, Xindong Wang, Xin'an Key Lab. of Integrated Microsystems Science Engineering and Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9780769548586

Runtime system-level power estimation is essential for dynamic power adaptation in integrated circuits. Indirect power estimation using a CPU performance monitoring unit (PMU) is widely used in modern microprocessors for its low cost. However, the existing CPU PMUs only monitor the activities of core and cache, resulting in accuracy limitation in power estimation for systems containing heterogeneous devices. In this paper, an on-chip bus PMU (OCB PMU) is proposed for PKU-DSPII SOC to achieve accurate system-level power estimation by taking range of peripheral devices into account. By monitoring the on-chip bus signals which indicate almost all the information of the system behavior, an OCB PMU is able to recognize different types of devices. By imitating the internal behavior of every device triggered by OCB signals using an energy state machine (ESM), an OCB PMU is capable of accurate power estimation of heterogeneous devices with complicated behavior. The proposed PMUs can also flexibly adapt to different SoC architectures. © 2012 IEEE.

关键词： System-on-chip

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FPGA implementation and verification system of H.264/AVC encoder for HDTV applications

FPGA implementation and verification system of H.264/AVC enc...

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Computer science and Information engineering, CSIE 2012

作者： Wang, Teng Chen, Chih-Kuang Yang, Qi-Hua Wang, Xin-An Key Lab. of Integrated Microsystems Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9783642302220

For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time encoding for HDTV applications (720P@60fps) with a PSNR around 34 db. The encoder was finally implemented with SMIC 65nm CMOS technology for silicon verification. © 2012 Springer-Verlag GmbH.

关键词： Field programmable gate arrays (FPGA)

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Semantic classification based clothing image retrieval

Semantic classification based clothing image retrieval

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2012 3rd IEEE/IET International Conference on Audio, Language and Image Processing, ICALIP 2012

作者： Lu, Zhiyuan Shen, Ling Yuan, Yule Zhao, Yong Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781467301718

Performance of content-based image retrieval technology used in clothing image retrieval cannot meet user's requirement due to the 'semantic gap' between low-level visual features and the richness of human semantics and it's time consuming to searching images in a growing number on the internet. In order to reduce the 'semantic gap' and improve the searching speed, this paper introduces a novel clothing image retrieval method based on color semantic classification. In this method, database images are classified into different categories with color semantic features and indexed by their visual features. In the retrieval process, images with the same semantic category are selected as candidates and further ranked by their visual features. The sematic information can also be used integrated with text information lab.led on the internet. Experimental results demonstrate our proposed method provides promising retrieval performance in less time than previous methods. © 2012 IEEE.

关键词： Semantics

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Design and implementation of a novel programmable power monitor chip

Design and implementation of a novel programmable power moni...

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2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010

作者： Ge, Binjie Wang, Xin'an Zhang, Xing Feng, Xiaoxing Wang, Qingqin Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781424467372

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.

关键词： Signal processing

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Operator design methodology and implementation for H.264 entropy encoder

Operator design methodology and implementation for H.264 ent...

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International Conference on Information engineering and Computer science

作者： Hu, Ziyi Chen, Kuilin Wang, Xin'an Key Lab. of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China

ISBN: (纸本)9781424479412

Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to logic gate level, the size of standard cells in digital circuits is increasing correspondingly. New methodology should be proposed to meet the need for shorter time-to-market IC industry, and the requirement of advanced IC manufacturing technology. This paper proposed the concept and principle of operator design methodology, then focused on the entropy coding application by the reconfigurable operator and finally gave the synthesis data. The results show that compared with the hardware design at the same cost of resources, this methodology can obtain hardware of suitable performance with regular structure. What is more, it can improve the design speed efficiently. ©2010 IEEE.

关键词： Entropy

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Dynamic Context Management for Coarse-grained Reconfigurable Array DSP Architecture

Dynamic Context Management for Coarse-grained Reconfigurable...

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IEEE 8th International Conference on ASIC

作者： Liu, Yanliang Dai, Peng Wang, Xin'an Zhang, Xing Wei, Lai Zhou, Yan Sun, Yachun Peking University Shenzhen Graduate School China Key Lab. of Integrated Microsystem Science and Engineering Applications China

ISBN: (纸本)9781424438686

This paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. The technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. The proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18um CMOS process mainly for multi-media applications(1).

关键词： Coarse-grained Reconfigurable Array DSP Architecture Context switch Context reuse Runtime reconfiguration (RTR) Partially Reconfiguration

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