Scale Invariance Feature Transform (SIFT) is quite suitable for image matching because of its invariance to image scaling, rotation and slight changes in illumination or viewpoint. However, due to high computation com...
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Scale Invariance Feature Transform (SIFT) is quite suitable for image matching because of its invariance to image scaling, rotation and slight changes in illumination or viewpoint. However, due to high computation complexity it's technically challenging to deploy SIFT in real time application situations. To address this problem, we propose CLSIFT, an OpenCL based highly speeded up and performance portable SIFT solution. Important optimization techniques employed in CLSIFT such as: (1) For less global memory traffic, independent logical functions are merged into the same kernel to reuse data. (2) loop buffers are introduced in for data and intermediate results reusing. (3)Task queue used to schedule threads in the same branch to remove branch divergences. (4) Data partition is based on the statics patterns for workload balance among workgroups. (5) Overlap of CPU time and better parallel strategies are used too. With all mentioned efforts, CLSIFT processes lena. jpg at 74.2 FPS and 43.4FPS respectively on NVidia and AMD GPUS, much higher than CPU's nearly 10 FPS and the known fastest SIFTGPU's 39.8 FPS and 13FPS. Moreover in a quantitative comparison approach we analyze those successful strategies beating SIFTGPU, a famous existing GPU implementation. Additionally, we observe and conclude that NVidia GPU achieves better occupancy and performance due to some factors. Finally, we summarize some techniques and empirical guiding principles that may be shared by other applications on GPU.
To make full use of the damping control capability of doubly-fed induction generators (DFIGs) and simultaneously minimize the detrimental impact on torsional oscillations of DFIGs. A hybrid power modulation PSS (HPM-P...
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ISBN:
(纸本)9781479913022
To make full use of the damping control capability of doubly-fed induction generators (DFIGs) and simultaneously minimize the detrimental impact on torsional oscillations of DFIGs. A hybrid power modulation PSS (HPM-PSS) combining both reactive power modulation (RPM) and active power modulation (APM) using the same feedback input signal is first proposed. Here the RPM part has the priority as it has little influence on torsional oscillations of DFIGs and APM part is complementary to further increase system damping to the objective value. Then a step by step optimization algorithm is developed to tune HPM-PSS parameters. The effectiveness of HPM-PSS is demonstrated by time-domain simulations and Prony analysis under different operation states and power control modes of the DFIG in a two-area test system.
This study deals with the performance analysis of time division broadcast (TDBC) protocol with channel estimation errors. The tight lower bounds for individual and system outage probabilities are first presented in cl...
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ISBN:
(纸本)9781467363686
This study deals with the performance analysis of time division broadcast (TDBC) protocol with channel estimation errors. The tight lower bounds for individual and system outage probabilities are first presented in closed-form. It is shown that the presence of channel estimation error causes outage probability to maintain a fixed level even when a noiseless channel is adopted. Simulation results validate the accuracy of our analytical results. Furthermore, comparison of signal-to-noise ratio (SNR) gap ratio shows that TDBC protocol is less sensitive to the effect of channel estimate error than analog network coding (ANC) protocol.
In this paper, we perform sparse signal analysis by using the Ramanujan Sums (RS). The RS are orthogonal in nature and therefore offer excellent energy conservation. Our analysis shows that the RS can compress the ene...
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Many-core SoC (MCSoC) design is one of chip design trends and challenges. Modeling and simulation for large scale MCSoC design is the key to get it right the first time. NoC is the most important component of future M...
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Many-core SoC (MCSoC) design is one of chip design trends and challenges. Modeling and simulation for large scale MCSoC design is the key to get it right the first time. NoC is the most important component of future MCSoC. A novel modeling tool, MCVP-NoC (Many-Core Virtual Platform with Networks-on-Chip support) was designed for large scale MCSoC modeling, and can be used in design space exploration, early software development and system verification. MCVP-NoC was built on systemC, OVP(Open Virtual Platform) and TLM2.0, integrated with Orion2.0 for power and area estimation. MCVP-NoC can run real software code, and can be used to evaluate the performance of the MCSoC design under real application load.
Frequent itemsets, also called frequent patterns, are important information about databases, and mining efficiently frequent itemsets is a core problem in data mining area. Pattern growth approaches, such as the class...
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In the Web Service world, it is an important technique that taking the usable behaviors in the existed web services provides some value-added functions by the service composition. Therefore, the usability analysis of ...
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LLE is a nonlinear dimensionality reduction method, which has been successfully applied to data visualization. Based on the assumption of local linearity, LLE can compute the weights between the KNN nodes using the lo...
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Gesture inputs on multi-touch tabletops usually involve multiple fingers (more than two) and casual touchdowns or liftoffs of fingers. This flexibility of touch gestures allows more natural user interaction, but also ...
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As the volumes of web images have grown rapidly in the last decade, Content-Based Image Retrieval (CBIR) has attracted substantial interests as an effective tool to manage the images. Most existing CBIR systems focus ...
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