An online semi-supervised active learning algorithm is proposed, which is based on self-organizing incremental neural network (SOINN). The proposed method do not need any priori knowledge such as number of nodes or nu...
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This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ...
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Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test applic...
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Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.
As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise consi...
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As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise considering multiple coupling effects and propose a novel test generation technique for this problem. A multiple crosstalk-induced glitch fault (MCGF) model is introduced, which gives information on one or more sub-paths to be sensitized to generate transitions coupled to a victim line. The test for an MCGF is a 2-vector pattern that sensitizes the transition signal along the sub-path to each aggressor line at the maximum aggressive time (MAT), and propagates the signal on a victim line to an output. A new structure, transition map (TM), is proposed to record all the possible arrival time of a line. The MAT of a victim line is calculated based on effective coupling capacitance (ECC). Therefore, the crosstalk-induced effects can be effectively identified, and exactly activated using the generated test patterns. Experiments on ISCAS89 benchmark circuit show that the proposed technique can be applied to circuits of reasonable sizes within acceptable time.
As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performan...
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As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8％ degradation with negligible computing time.
In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may mak...
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In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30％ of the sensors are faulty, over 95％ of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.
Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the in...
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Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.
The continuous development of VLSI technology is shrinking the minimal sizes to nanometer region, making circuits more susceptible to transient error. In this paper, we present a frequency analysis method to accur...
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The continuous development of VLSI technology is shrinking the minimal sizes to nanometer region, making circuits more susceptible to transient error. In this paper, we present a frequency analysis method to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We use the frequency feature of signal and frequency response of electrical system to analyze the propagation of transient error. Experiments show that on average, our approach provides approximately 95％ accuracy and several orders of magnitude faster with respect to HSPICE simulation.
This paper presents a data placement of a two-disk failure-tolerant disk arrays system, a code-mixing solution RAID5x with XOR-based code and mirror for disk arrays to improve performance of accessing storage system w...
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Disk mirroring or RAID1 is a popular paradigm to achieve fault tolerance and high reliability, this paper describes four mirrored disk organizations: basic mirroring, group rotate declustering, interleaved declusterin...
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