The increasing complexity of systems poses a big challenge to design systems with fault-tolerant *** aim of this study was to establish fault-tolerant system for multiprocessor platform with the help of hierarchical s...
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ISBN:
(纸本)9781629931357
The increasing complexity of systems poses a big challenge to design systems with fault-tolerant *** aim of this study was to establish fault-tolerant system for multiprocessor platform with the help of hierarchical scheduling framework.A mathematical fault and reliability model for hierarchical scheduling framework was proposed firstly,and then a heuristic algorithm by exploiting the difference of task resource overhead and the probability of task failures was presented and a task replication scheme was given *** experimental results demonstrated the proposed scheme could effectively guarantee reliability goal and reduce resource consumption simultaneously.
Masking in gate level could efficiently protect AES S-box out of power analysis attack. But there still exists a kind of attack, called glitch attack, to achieve the sensitive information from gate cell leakage. Some ...
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Recently, there is a new kinds of cryptographic algorithms are proposed to meet the requirements of "lightweight" applications. PRESENT is one of them, which is built based on 4-bit substitution transformati...
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Masking in gate level is popularly used to protect AES S-box against power analysis attacks. But there still exists a kind of attack, called glitch attack, to achieve the sensitive information from gate cell leakage. ...
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Masking in gate level is popularly used to protect AES S-box against power analysis attacks. But there still exists a kind of attack, called glitch attack, to achieve the sensitive information from gate cell leakage. Some works had been done to resist against glitch attack, which carefully masked AND gate or used Wave Dynamic Differential Logic (WDDL) cell. In this paper, we propose an improved masked AND gate, in which the relationship between input masked values and masks is nonlinear. Usually, when converting S-box operations from GF(28) to GF(((22)2)22), all the necessary computations become XOR and AND operations. Therefore, to fully mask AES S-box is to substitute the unmasked XOR and AND operations with the proposed masked AND gate and protected XOR gate. Although the proposed masked AND gate take up one extra XOR gate than Trichina's design and Baek's design, it can resist against glitch attack without using specific gate cell, such as WDDL. Finally with the masked AES Sbox, we provide a probable secure implementation of masked AES encryption with 32-bit data and verify the results.
In the recent years, embedded systems began to be used in sensitive applications such as personal digital assistants and smart cards. Due to very strict cost and power constrains, the support for cryptography provided...
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In the recent years, embedded systems began to be used in sensitive applications such as personal digital assistants and smart cards. Due to very strict cost and power constrains, the support for cryptography provided...
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In the recent years, embedded systems began to be used in sensitive applications such as personal digital assistants and smart cards. Due to very strict cost and power constrains, the support for cryptography provided by these devices is often limited to either public or private key primitives. This limitation is much more evident in devices where the cryptographic algorithms are implemented using hardware resources. In this paper, we propose an extension of a public-key cryptosystem to support also private-key, and we evaluate our architecture on FPGA platforms. In particular, we propose a new arithmetic unit in which the polynomial modular multiplication of ECC is extended to compute also the polynomial arithmetic operations over binary extended field of AES. We compare our design with an architecture obtained by instantiating state of the art implementation of AES and ECC and we evaluate the trade-offs. The experimental results show that our proposed architecture takes up less hardware resources. Nevertheless, the achieved performances are better compared to the ECC reference core, while the ones compared to AES only implementation are comparable with the state of the art.
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