Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still ...
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Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor （DSP）, and application specific integrated circuit （ASIC） and field programmable gate array （FPGA） provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.
The quality of virtual view based on multi-view video （MVD） plus depth format is often evaluated by PSNR or subjectively judged. However, due to synthesizing arbitrary view images, the virtual view images mostly hav...
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The quality of virtual view based on multi-view video （MVD） plus depth format is often evaluated by PSNR or subjectively judged. However, due to synthesizing arbitrary view images, the virtual view images mostly have no reference images and are only assessed using non-reference. Virtual view images synthesized by depth estimation reference software （DERS） and view synthesis reference software （VSRS） often accompanied with blockiness and other distortions on the edge. In addition, matching level for the depth map and the corresponding texture maps of left and right views also affects the quality of the virtual view. This paper compares the edge similarity of the depth and the corresponding texture maps which generate the intermediate virtual view and combined with the virtual view＇s blockiness which causing blur to evaluate the quality of the virtual view. Experiment results show that the proposed method can reflect the quality of the virtual view better.
Depth maps are used for synthesis virtual view in free-viewpoint television （FTV） systems. When depth maps are derived using existing depth estimation methods, the depth distortions will cause undesirable artifacts ...
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Depth maps are used for synthesis virtual view in free-viewpoint television （FTV） systems. When depth maps are derived using existing depth estimation methods, the depth distortions will cause undesirable artifacts in the synthesized views. To solve this problem, a 3D video quality model base depth maps （D-3DV） for virtual view synthesis and depth map coding in the FTV applications is proposed. First, the relationships between distortions in coded depth map and rendered view are derived. Then, a precisely 3DV quality model based depth characteristics is develop for the synthesized virtual views. Finally, based on D-3DV model, a multilateral filtering is applied as a pre-processed filter to reduce rendering artifacts. The experimental results evaluated by objective and subjective methods indicate that the proposed D-3DV model can reduce bit-rate of depth coding and achieve better rendering quality.
With the continual increase in cooling demand for microprocessors, the microelectronics industry has been increasingly focused on the development of thermal solutions. Thermal Interface Material (TIM) plays a key role...
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With the continual increase in cooling demand for microprocessors, the microelectronics industry has been increasingly focused on the development of thermal solutions. Thermal Interface Material (TIM) plays a key role in reducing the thermal resistance of packaging and the thermal resistance between the electronic device and the external cooling components. Nano-TIM, a new type of thermal interface material, was developed to improve the heat dissipation of electronic devices. This paper describes work undertaken to research the reliability of Nano-TIM. Pull tests were used to investigate the shear strength of samples with Nano-TIM of different thicknesses coalesced between two PCBs with Sn coating made under different pressure. Scanning Electron Microscopy (SEM) analysis techniques were used to determine the morphology of the shear fracture section after pull tests and observe the structure of the cross section of Nano-TIM coalesced between two PCBs with Sn coating.
This paper presents the design and logic implementation of the fractal scan algorithm based on the mathematical model of the optimal scan architecture. Through the exploration of the sub-space code sequences and bit c...
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We have developed a new method to measure the water vapor transmission ratio (WVTR) for thin film encapsulation (TFE) of organic light emitting diodes (OLEDs). It is a nondestructive method to measure WVTR by investig...
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We have developed a new method to measure the water vapor transmission ratio (WVTR) for thin film encapsulation (TFE) of organic light emitting diodes (OLEDs). It is a nondestructive method to measure WVTR by investigating the change of photoluminescent spectra of organic material. This method can be realized easily by online test. By calibrating the evolution curve (the photoluminescent intensity versus time), we have figured out the relative water transmission which was responded by organic materials. The WVTR of TFE devices is estimated to be about 2.0×10-2gm-2day-1 in a controlled environment of 85% relative humidity (RH) at 38℃. Novel thin film encapsulation devices have also been presented.
Limited by the toxicity of Pb and Pb-containing compounds and the implementation of the mandatory legislations, such as WEEE and RoHS, the Pb-containing solders have been banned and accordingly the Pb-free solders hav...
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Limited by the toxicity of Pb and Pb-containing compounds and the implementation of the mandatory legislations, such as WEEE and RoHS, the Pb-containing solders have been banned and accordingly the Pb-free solders have become popular in electronic industry. However, the novel developed Pb-free solders could cause a series of packaging defects such as delamination, cracking, and charring etc. due to the relatively high melting temperatures of these Pb-free substitutes compared to the former Sn-Pb
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