MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory...
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MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.
In this paper, we describe a comprehensive study conducted to understand the methodologies which are being used to design intelligent Decision Support Systems (IDSSs) and to identify the key methodological problems an...
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In this paper, we describe a comprehensive study conducted to understand the methodologies which are being used to design intelligent Decision Support Systems (IDSSs) and to identify the key methodological problems and benefits with using these methodologies. This comprehensive study consists of two parts. The first part is two surveys which together identify the design methodologies being used by a group of IDSS developers and how acceptable they believe their methodologies were for designing their IDSSs. The second part is a comparison of six major formal IDSS design methodologies recently published in the literature and which are not yet known to many developers. This paper is presented to assist IDSS developers in understanding what support can be gained from using existing design methodologies and hence choose the correct one for their project. Furthermore, the paper may be used by IDSS developers to compare the way that they work with the approach proposed by other developers. (C) 1997 Elsevier Science B.V.
Hardware description language (HDL) code designing is a critical component of the chip design process, requiring substantial engineering and time resources. Recent advancements in large language models (LLMs), such as...
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Hardware description language (HDL) code designing is a critical component of the chip design process, requiring substantial engineering and time resources. Recent advancements in large language models (LLMs), such as GPT series, have shown promise in automating HDL code generation. However, current LLM-based approaches face significant challenges in meeting real-world hardware design requirements, particularly in handling complex designs and ensuring code correctness. Our evaluations reveal that the functional correctness rate of LLM-generated HDL code significantly decreases as design complexity increases. In this paper, we propose the AutoSilicon framework, which aims to scale up the hardware design capability of LLMs. AutoSilicon incorporates an agent system, which 1) allows for the decomposition of large-scale, complex code design tasks into smaller, simpler tasks; 2) provides a compilation and simulation environment that enables LLMs to compile and test each piece of code it generates; and 3) introduces a series of optimization strategies. Experimental results demonstrate that AutoSilicon can scale hardware designs to projects with code equivalent to over 10,000 tokens. In terms of design quality, it further improves the syntax correctness rate and functional correctness rate compared with approaches that do not employ any extensions. For example, compared to directly generating HDL code using GPT-4-turbo, AutoSilicon enhances the syntax correctness rate by an average of 35.8% and improves functional correctness by an average of 35.6%.
Connected Autonomous Vehicle (CAV) Driving, as a data-driven intelligent driving technology within the Internet of Vehicles (IoV), presents significant challenges to the efficiency and security of real-time data manag...
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Connected Autonomous Vehicle (CAV) Driving, as a data-driven intelligent driving technology within the Internet of Vehicles (IoV), presents significant challenges to the efficiency and security of real-time data management. The combination of Web3.0 and edge content caching holds promise in providing low-latency data access for CAVs’ real-time applications. Web3.0 enables the reliable pre-migration of frequently requested content from content providers to edge nodes. However, identifying optimal edge node peers for joint content caching and replacement remains challenging due to the dynamic nature of traffic flow in IoV. Addressing these challenges, this article introduces GAMA-Cache, an innovative edge content caching methodology leveraging Graph Attention Networks (GAT) and Multi-Agent Reinforcement Learning (MARL). GAMA-Cache conceptualizes the cooperative edge content caching issue as a constrained Markov decision process. It employs a MARL technique predicated on cooperation effectiveness to discern optimal caching decisions, with GAT augmenting information extracted from adjacent nodes. A distinct collaborator selection mechanism is also developed to streamline communication between agents, filtering out those with minimal correlations in the vector input to the policy network. Experimental results demonstrate that, in terms of service latency and delivery failure, the GAMA-Cache outperforms other state-of-the-art MARL solutions for edge content caching in IoV.
The advancement of the Internet of Medical Things (IoMT) has led to the emergence of various health and emotion care services, e.g., health monitoring. To cater to increasing computational requirements of IoMT service...
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The advancement of the Internet of Medical Things (IoMT) has led to the emergence of various health and emotion care services, e.g., health monitoring. To cater to increasing computational requirements of IoMT services, Mobile Edge computing (MEC) has emerged as an indispensable technology in smart health. Benefiting from the cost-effectiveness of deployment, unmanned aerial vehicles (UAVs) equipped with MEC servers in Non-Orthogonal Multiple Access (NOMA) have emerged as a promising solution for providing smart health services in proximity to medical devices (MDs). However, the escalating number of MDs and the limited availability of communication resources of UAVs give rise to a significant increase in transmission latency. Moreover, due to the limited communication range of UAVs, the geographically-distributed MDs lead to workload imbalance of UAVs, which deteriorates the service response delay. To this end, this paper proposes a UAV-enabled Distributed computation Offloading and Power control method with Multi-Agent, named DOPMA, for NOMA-based IoMT environment. Specifically, this paper introduces computation and transmission queue models to analyze the dynamic characteristics of task execution latency and energy consumption. Moreover, a credit assignment scheme-based reward function is designed considering both system-level rewards and rewards tailored to each MD, and an improved multi-agent deep deterministic policy gradient algorithm is developed to derive offloading and power control decisions independently. Extensive simulations demonstrate that the proposed method outperforms existing schemes, achieving \(7.1\%\) reduction in energy consumption and \(16\%\) decrease in average delay.
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