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A 10-kHz 12–16-bit reconfigurable zoom ADC with pole optimization technique and floating current-starved amplifier

Science China(Information Sciences) 2024年第12期67卷 341-342页

作者： Zhangming ZHU Jiajun SONG Yuhua LIANG Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education) School of Integrated CircuitsXidian University

Recently, zoom analog-to-digital converters(ADCs) have been shown to be well-suited for reconfigurable ADCs. They achieve high resolution and high energy efficiency by combining the advantages of the successive approx...

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A Background Calibration Method of Bandwidth Mismatch for Time-Interleaved ADCs Based on Neural Network 17

A Background Calibration Method of Bandwidth Mismatch for Ti...

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17th IEEE International Conference on Solid-State and integrated Circuit Technology, ICSICT 2024

作者： Yang, Tianqi Wang, Longsheng Zhao, Xin Liu, Shubin Li, Dengquan Zhu, Zhangming School of Integrated Circuits Xidian University Key Laboratory of Analog Integrated Circuits and Systems Ministry of Education China

ISBN: (纸本)9798350361834

This paper proposes a background calibration algorithm based on neural network (NN) for bandwidth mismatch in TI-ADCs. The calibration method uses a three-layer neural network to achieve lower training resource consumption and higher calibration accuracy by processing the input and target output data of the TI-ADC. The optimal structure of the neural network is determined by simulation. A 12-bit, 3.2GS/s TI-ADC model is used to validate our proposed method. Simulation results show that SNDR and SFDR are improved from 49.75dB and 53.37dB to 69.51dB and 88.75dB after calibration, respectively. The calibration method provides good calibration performance for different types of signals, including single-tone and multi-tone signals, and it is applicable over a wide frequency range. Meanwhile, it has a high effective bandwidth that covers the overall Nyquist frequency range. © 2024 IEEE.

关键词： Calibration

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Background Calibration for Bit Weights in Pipelined SAR ADCs Using Split ADC Architecture 17

Background Calibration for Bit Weights in Pipelined SAR ADCs...

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17th IEEE International Conference on Solid-State and integrated Circuit Technology, ICSICT 2024

作者： Zhou, Zecheng Wang, Longsheng Ye, Dongxian Zhu, Yexin Li, Dengquan Zhu, Zhangming School of Integrated Circuits Xidian University Key Laboratory of Analog Integrated Circuits and Systems Ministry of Education China

ISBN: (纸本)9798350361834

A background calibration method of bit weights for pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs) is presented. The method corrects the errors from capacitor mismatch and inter-stage gain error. The ADC is split into two independent converters, each converting the same input signal. The dither window is constructed by adding opposite polarity offsets to each comparator of the converters to obtain the bit weights. Simulation results show that after 2×105 cycles, the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are improved from 54.1dB to 69.9dB and 63.8dB to 95.6dB, respectively. The proposed calibration method has the advantages of high accuracy, fast convergence speed and running in background. © 2024 IEEE.

关键词： Calibration

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A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting 20

A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noi...

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20th IEEE Asia Pacific Conference on circuits and systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024

作者： Huang, Yiyao Fu, Guolong Zhang, Xianghui Zhang, Yanbo Liu, Shubin Zhu, Zhangming Xidian University Key Laboratory of Analog Integrated Circuits and Systems Xi'an China

ISBN: (纸本)9798350378771

Oriented at achieving high resolution and power efficiency, the noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is a popular architecture. Although the thriving NS-SAR ADC can shape the quantization error, the loop filters do not contribute to suppressing noise during sampling, which is usually settled by utilizing large capacitors. This paper presents a second-order NS-SAR ADC with kT/C noise shifting, which exploits the errorfeedback (EF) structure to realize aggressive noise-shaping and substantially reduces the input capacitor size without the large kT/C noise penalty. Implemented in 180-nm CMOS, this work achieves 91-dB signal-to-noise ratio (SNR) and 89.5-dB signal-to-noise-distortion ratio (SNDR) with 417-kHz bandwidth (BW). It uses merely 0.246 -pF input capacitance, which is 6.5 x smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR. © 2024 IEEE.

关键词： Signal to noise ratio

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A 0.9-V Supply Up to 21.5-dB Boost Gain analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End wit...

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2024 IEEE International Conference on integrated circuits, Technologies and Applications, ICTA 2024

作者： Zhang, Miao Su, Xianting Yang, Zekai Dong, Zhicheng Huang, Weitan Wang, Menghao Yu, Yukui Zhao, Xiaoteng Liu, Shubin Zhu, Zhangming Xidian University Key Laboratory of Analog Integrated Circuits School of Integrated Circuits China

ISBN: (纸本)9798331530709

This paper presents an analog front-end (AFE) circuit for 112-Gb/s four-level pulse amplitude modulation (PAM-4) medium-reach (MR) receivers. To ensure sufficient bandwidth and enhance boost gain, the AFE employs of a cascaded architecture of two stages of continuous-time linear equalizer (CTLE) and three stages of variable gain amplifier (VGA). Both the CTLE and VGA are loaded with T-coils to extend the bandwidth, enabling the AFE to operate at a standard voltage of 0.9 V without a dedicated regulator. Eight parameters are adopted to tune the high, medium, and low-frequency-bands response to match loss profiles well for MR channels. Post-layout simulations in 28-nm CMOS technology demonstrate that the proposed AFE achieves a gain boost of up to 21.5 dB dissipating 43.8 mW at a 0.9V supply, achieving larger than 28-GHz bandwidth within the area of 0.06 ∼mm2. When combined with an ideal 4-tap feed-forward equalizer (FFE) from the transmitter, the proposed AFE achieves a symbol error rate (S E R)-12 at 112 ∼Gb / s using 2 15-1 PRBS PAM-4 pattern with a 19.5-dB channel loss at 28 GHz. © 2024 IEEE.

关键词： Variable gain amplifiers

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Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning

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IEEE Transactions on Computer-Aided Design of integrated circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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A Fast Two-Tone Active Load-Pull Algorithm for Assessing the Non-linearity of RF Devices

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Chinese Journal of Electronics 2022年第1期31卷 25-32页

作者： SU Jiangtao CAI Jialing ZHENG Xing SUN Lingling Key Laboratory of RF Circuits and Systems Ministry of Education Key Laboratory of Large Scale Integrated Circuits Design Zhejiang Province

Radio frequency(RF) devices used in modern wireless systems must meet increasingly complicated spectral constraints while still operating with high power efficiency. A fast real-time two-tone active loadpull algorithm is proposed to assess the relationship between nonlinear performance with associated device load impedance variations. This algorithm employs real time measurement data to extract two-tone local nonlinear behaviour model, which is further used for the prediction of injected signal value in the active real-time loadpull system, therefore minimizing the number of iterations required for load emulation. The proposed method was validated on a real two-tone load-pull measurement bench using off-the-shelf instruments. The result shows that the measurement speed has been greatly increased without sacrifice of the impedance emulation *** intelligent two-tone load-pull algorithm is expected to be applied in the designing of modern communication system and radar transmitters, as well as the validation of the models of radio frequency transistors.

关键词： measurement speed real-time load-pull system spectral constraints radio frequency transistors real time measurement data intelligent two-tone load-pull algorithm two-tone local nonlinear behaviour model radio frequency devices impedance emulation accuracy modern communication system modern wireless systems nonlinearity radiocommunication RF devices associated device load impedance variations radar transmitters injected signal value two-tone load-pull measurement bench load emulation high power efficiency fast real-time two-tone active load-pull algorithm nonlinear performance

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A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS

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Science China(Information Sciences) 2024年第8期67卷 347-348页

作者： Shubin LIU Chenxi HAN Xiaoteng ZHAO Yuhao ZHANG Shixin LI Hongzhi LIANG Lihong YANG Zhangming ZHU Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education) School of Integrated CircuitsXidian University

With the growing demand for communication bandwidth,transmitters(TXs) are operating at higher rates, compressing the timing margin for the last 4:1 or 2:1 multiplexer(MUX). To alleviate the timing constraints, the retimer is introduced before the last-stage MUX. However, owing to process, voltage, and temperature(PVT) variations, the phase relationship between the retiming clock and the input data is uncertain, leading to insufficient setup and hold time for the successive retimer.

关键词： CMOS integrated circuits

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Digitalized analog integrated circuits

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Fundamental Research 2024年第6期4卷 1415-1430页

作者： Zhangming Zhu Shubin Liu Shaanxi Key Laboratory of Integrated Circuits and Systems School of MicroelectronicsXidian UniversityXi’an 710071China

Digital integrated circuits have significantly benefited from technology scaling down,while conventional analog integrated circuits suffer from more design *** recent years,there has been strong research interest in replacing conventional analog blocks with digitally-friendly and digitally-intensive alternatives,while signif-icant progress has been *** paper reviews the existing digitalized analog integrated circuits,including amplifiers,analog-to-digital converters,phase-locked loops,and power *** on the review,the future development trends of the digitalized analog integrated circuits are derived.

关键词： analog integrated circuits Digitization Amplifier analog-to-digital converter Phase-locked loop Power supply

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A Review of Terahertz Solid-State Electronic/Optoelectronic Devices and Communication systems

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Chinese Journal of Electronics 2025年第1期34卷 26-48页

作者： Wenbo Li Hongxin Zeng Lin Huang Sen Gong Haoyi Cao Weipeng Wang Zheng Wang Hongji Zhou Shixiong Liang Ziqiang Yang Yaxin Zhang University of Electronic Science and Technology of China Huzhou Key Laboratory of Terahertz Integrated Circuits and Systems Yangtze Delta Region Institute (Huzhou)University of Electronic Science and Technology of China Terahertz Institute Zhangjiang National Laboratory National Key Laboratory of Application Specific Integrated Circuit Hebei Semiconductor Research Institute

With the rapid development of modern communication technology, spectrum resources have become non-renewable and precious resources, and the terahertz frequency band has entered people's vision. Nowadays, terahertz communication technology has become one of the core technologies for future high-capacity and high-rate communication. This paper discusses and analyzes the core technologies related to the field of terahertz *** introduce the characteristics, domestic and international comparisons and development trends of the core devices for terahertz communication, and also introduce and discuss the terahertz solid-state frequency mixing communication system, terahertz direct modulation communication system, and terahertz optoelectronic communication ***, we summarize the development of terahertz communication technology and the outlook of future applications.

关键词： Frequency modulation Reviews Solids Market research Terahertz communications

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