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IMPULP:A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

Journal of computer Science & Technology 2020年第2期35卷 418-432页

作者： Yang-Yang Zhao Ming-Yu Chen Yu-Hang Liu Zong-Hao Yang Xiao-Jing Zhu Zong-Hui Hong Yun-Ge Guo State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China

In recent years many security attacks occur when malicious codes abuse in-process memory *** to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security *** a result,the users have the risk of suffering information leakage and control flow ***,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security *** this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory *** rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary *** instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be *** can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory *** verification,an FPGA prototype based on RISC-V instruction set architecture has been *** present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security *** execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of *** performance overhead of IMPULP is less than 0.2%runtime on average,which is ***,the resource overhead is less than 5.5%for hardware modification of IMPULP.

关键词： in-process isolation memory protection out-of-bounds user-level partitioning

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Labeled yon Neumann architecture for Software-Defined Cloud

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Journal of computer Science & Technology 2017年第2期32卷 219-223页

作者： Yun-Gang Bao Sa Wang, Member, CCF State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

As cloud computing is moving forward rapidly, cloud providers have been encountering great challenges： long tail latency, low utilization, and high interference. They intend to co-locate multiple workloads on a single server to improve the resource utilization. But the co-located applications suffer from severe performance interference and long tail latency, which lead to unpredictable user experience. To meet these challenges, software-defined cloud has been proposed to facilitate tighter coordination among application, operating system and hardware. Users＇ quality of service （QoS） requirements could be propagated all the way down to the hardware with differential management mechanisms. However, there is little hardware support to maintain and guarantee users＇ QoS requirements. To this end, this paper proposes Labeled von Neumann architecture （LvNA）, which introduces a labelling mechanism to convey more software＇s semantic information such as QoS and security to the underlying hardware. LvNA is able to correlate labels with various entities, e.g., virtual machine, process and thread, and propagate labels in the whole machine and program differentiated services based on rules. We consider LvNA to be a fundamental hardware support to the software-defined cloud.

关键词： software-defined cloud von Neumann architecture tail latency performance interference

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

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Tsinghua Science and Technology 2007年第S1期12卷 95-100页

作者：阚保强蔡理徐勇军 College of Science Air Force Engineering University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Low-power design is one of the most important issues in wireless sensor networks (WSNs) , while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error–rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Journal of computer Science & Technology 2009年第6期24卷 1086-1097页

作者：米伟冯晓兵贾耀仓陈莉薛京灵 Key Laboratory of Computer System and Architecture Institution of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.

关键词： DRAM row buffer page allocation locality optimization

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Efficient Algorithm for Energy-Aware Virtual Network Embedding

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Tsinghua Science and Technology 2016年第4期21卷 407-414页

作者： Shuxian Jia Guiyuan Jiang Peilan He Jigang Wu School of Computer Software Technology Zhejiang University Ningbo 315048 China School of Computer Science and Engineering Nanyang Technological University 639798 Singapore State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Network virtualization is a promising approach for resource management that allows customized Virtual Networks （VNs） to be multiplexed on a shared physical infrastructure. A key function that network virtualization can provide is Virtual Network Embedding （VNE）, which maps virtual networks requested by users to a shared substrate network maintained by an Internet service provider. Existing research has worked on this, but has primarily focused on maximizing the revenue of the Internet service provider. In this paper, we consider energy-aware virtual network embedding, which aims at minimizing the energy consumption for embedding virtual networks in a substrate network. In our optimization model, we consider energy consumption of both links and nodes. We propose an efficient heuristic to assign virtual nodes to appropriate substrate nodes based on priority, where existing activated nodes have higher priority for hosting newly arrived virtual nodes. In addition, our proposed algorithm can take advantage of activated links for embedding virtual links so as to minimize total energy consumption. The simulation results show that, for all the cases considered, our algorithm can improve upon previous work by an average of 12.6% on acceptance rate, while the consumed energy can be reduced by 12.34% on average.

关键词： virtualization technology virtual network embedding energy efficient optimization algorithm

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A decomposition based algorithm for maximal contractions

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Frontiers of computer Science 2013年第6期7卷 801-811页

作者： Dongchen JIANG Wei LI Jie LUO Yihua LOU Zhengzhong LIAO State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China Tencent Technology (Beijing) Company Limited Beijing 100080 China

This paper proposes a decomposition based algo- rithm for revision problems in classical propositional logic. A set of decomposing rules are presented to analyze the satis- fiability of formulas. The satisfiability of a formula is equivalent to the satisfiability of a set of literal sets. A decomposing function is constructed to calculate all satisfiable literal sets of a given formula. When expressing the satisfiability of a formula, these literal sets are equivalent to all satisfied models of such formula. A revision algorithm based on this decomposing function is proposed, which can calculate maximal contractions of a given problem. In order to reduce the memory requirement, a filter function is introduced. The improved algorithm has a good performance in both time and space perspectives.

关键词： belief change maximal contraction decomposing rules revision algorithm

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DoCE: Direct extension of on-chip interconnects over converged ethernet for rack-scale memory sharing 1

DoCE: Direct extension of on-chip interconnects over converg...

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1st Workshop on Emerging Technologies for Software-Defined and Reconfigurable Hardware-Accelerated Cloud Datacenters, ETCD 2017 - Held in conjunction with 22nd ACM ASPLOS

作者： Chang, Yisong Zhao, Ran Yu, Lei Zhang, Ke State Key Laboratory of Computer Architecture ICT CAS Beijing100190 China

ISBN: (纸本)9781450349239

Novel rack-level interconnects are urgently required to support frequent inter-server communications in emerging large-scale distributed in-memory applications. In this paper, we introduce DoCE, a memory semantic fabric via Direct extension of on-chip interconnect (DEOI) over Converged Ethernet. Based on the architectural support for fine-grained remote memory sharing, DoCE provides a 9.6x speedup for distributed implementation of PageRank algorithm on our dual-node ARM SoC-FPGA prototype versus a conventional TCP/IP based solution. To the best of our knowledge, DoCE is the first implementation and prototype for memory semantic fabric via existing Ethernet infrastructure in ARM ecosystem. © 2016 ACM.

关键词： Ethernet

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A Non-Stop Double Buffering Mechanism for Dataflow architecture

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Journal of computer Science & Technology 2018年第1期33卷 145-157页

作者： Xu Tan Xiao-Wei Shen Xiao-Chun Ye Da Wang Dong-Rui Fan Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

关键词： non-stop double buffering dataflow architecture high-performance computing

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Using index in the MapReduce framework

Using index in the MapReduce framework

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12th International Asia Pacific Web Conference, APWeb 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9780769540122

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be nontrivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query. © 2010 IEEE.

关键词： MapReduce

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Memory Efficient Two-Pass 3D FFT Algorithm for Intel~ Xeon Phi^(TM) Coprocessor

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Journal of computer Science & Technology 2014年第6期29卷 989-1002页

作者：刘益群李焱张云泉张先轶 Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science and Technology Tsinghua University CCF ACM IEEE State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Equipped with 512-bit wide SIMD inst d large numbers of computing cores, the emerging x86-based Intel（R） Many Integrated Core （MIC） architecture ot only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT （three-di fast Fourier transform） is a widely-studied algorithm; however, the conventional algorithm needs to traverse the three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of rided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into ensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively erence in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. el parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of loc On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectoriz employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel（R） PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which ts the vendor-specific Intel（R）MKL library by a factor of up to 2.22X.

关键词： 3D-FFT memory efficie many-core Many Integrated Core Intel(R) Xeon PhiTM

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