Data uncertainty appears in many important XML applications. Recent probabilistic XML models represent different dependency correlations of sibling nodes by adding various kinds of distributional nodes, while there do...
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PLSA(Probabilistic Latent Semantic Analysis) is a popular topic modeling technique for exploring document collections. Due to the increasing prevalence of large datasets, there is a need to improve the scalability of ...
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NAND Flash memories have rapidly emerged as a storage class memory such as SSD (Solid State Disk), CF (Compact Flash) Card, SD (Secure Digital Memory) Card. Due to its distinct operation mechanisms, NAND Flash memory ...
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NAND Flash memories have rapidly emerged as a storage class memory such as SSD (Solid State Disk), CF (Compact Flash) Card, SD (Secure Digital Memory) Card. Due to its distinct operation mechanisms, NAND Flash memory suffers from erase/program endurance, data retention and program/read disturbance problems. Specifically, erase and program operation keeps in developing bad blocks during the lifetime of memory chips. Bad blocks are blocks that contain faulty bits but the ECC (Error Correction Code) algorithm cannot correct them. Although wear leveling tries to balance the erase/program operations on different blocks so that all blocks can wear out at a similar pace, new bad blocks still inevitably *** propose an in-field testing technique which takes some pages in a block as predictors. Due to wear out faster than the other pages, the predictors will become bad before the other pages in the block become bad. The further questions are (1) how to detect those wearing fast pages so as to use them as predictors, (2) how many predictors are needed to achieve a satisfactory prediction accuracy, (3) misprediction will result in what negative impact on performance and endurance.
To minimize Rate-Distortion (RD) cost in video coding, RD Optimization (RDO) technique is adopted, which also brings increasingly computational complexity in Motion Estimation (ME), multiple reference selection and mo...
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As biological systems exhibit adaptation, healing and robustness in the face of changing environmental behavior, this paradigm has actuated research dealing with the concept of self-healing systems, which attempt to h...
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As biological systems exhibit adaptation, healing and robustness in the face of changing environmental behavior, this paradigm has actuated research dealing with the concept of self-healing systems, which attempt to heal themselves in the sense of recovering from malicious attacks and rectifying of system faults. The goal of self-healing systems is to provide survivable systems that require high dependability, robustness, adaptability, and availability. Such systems maintain one or more models, whether external or internal, at run time as a basis for identifying problems and resolving them. This article describes an architectural description language, called ADML, which is being developed as a new formal language and/or conceptual model for representing evolving software architectures. The ADML embraces dynamic change as a fundamental consideration, supports a broad class of adaptive changes at the architectural level, and offers a uniform way to represent and reason about both static and dynamic aspects of self-healing systems. Because the ADML is based on the Dynamic Description Logic DDL(SHON (D)), which can represent both dynamic semantics and static semantics under a unified logical framework, architectural ontology entailment for the ADML languages can be reduced to knowledge base satisfiability in DDL(SHON (D)), and dynamic description logic algorithms and implementations can be used to provide reasoning services for ADML. In this article, we present the syntax of ADML, explain its underlying semantics using the Dynamic Description Logic DDL(SHON (D)), and exemplify our approach by applying it to the domain of load balancing a wireless remote-access system;the preliminary results certify the potential of the approach.
Chosen-ciphertext security has been well-accepted as a standard security notion for public key encryption. But in a multi-user surrounding, it may not be sufficient, since the adversary may corrupt some users to get t...
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In this paper, a novel concept of multilayer synthesis and a general framework for texture synthesis method are presented. Within this framework, we first decompose the texture into the supposed pattern layer and mate...
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In this paper, a novel concept of multilayer synthesis and a general framework for texture synthesis method are presented. Within this framework, we first decompose the texture into the supposed pattern layer and material layer in the frequency domain by an E-texton extracting algorithm, then manipulate and extend them respectively according to their own personalities, and finally merge the newly synthesized pattern layer and material layer again to generate the final output. Experiment results show that our method not only greatly improves the synthesis quality for those cases that single-layer synthesis cannot handle well but also provides an ability of achieving various special synthesis effects.
With the rapid development of service-oriented computing (SOC) and service-oriented architecture (SOA), the number of services is rapidly increasing. How to organize and manage services effectively in repositories to ...
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In this paper, we present a scalable implementation of a topic modeling (Adaptive Link-IPLSA) based method for online event analysis, which summarize the gist of massive amount of changing tweets and enable users to e...
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Moore＇s law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievemen...
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Moore＇s law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are smnmarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc.
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