In this paper,in order to increase the amount of hiding information,we choose MPEG sequences as carriers and present a practical method focus on the steganographic method in MPEG compressed video ***,there are many B-...
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In this paper,in order to increase the amount of hiding information,we choose MPEG sequences as carriers and present a practical method focus on the steganographic method in MPEG compressed video ***,there are many B-frames in each *** utilize the B-frames to hide information so that we can increase the amount of hiding information and decrease the tamper of the *** and extracting are performed in compressed video sequences without requiring original *** experimental results show that the proposed method has the characteristics of less tampering on the visual effect and larger hiding capacity without increasing the volume of the carrier file.
Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip inte...
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ISBN:
(纸本)9783981080186
Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Network-on-Chip (NoC) based multicore systems. In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. With clustering scheme, multiple concurrent trace sources can access distributed trace buffer via NoC under bandwidth constraint. We evaluate the proposed scheme using Booksim and the results show the effectiveness of the proposed scheme.
As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically...
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ISBN:
(纸本)9783981080186
As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically, the leakage power dissipated in the used part of FPGA device, which is known as the active leakage power. We observe that the leakage power in off-path transistors takes up most of the active leakage power in multiplexers that control routing, and strongly depends on Hamming distance between the state of the on-path input and the states of the off-path inputs. Hence, an off-path leakage power aware routing algorithm is proposed to minimize Hamming distance between the state of on-path input and the states of off-path inputs for each multiplexer. Experimental results on MCNC benchmark circuits show that, compared with the baseline VPR technique, the proposed off-path leakage aware routing algorithm can reduce active leakage power in routing resources by 16.79%, and the increment of critical-path delay is only 1.06%.
With the continual scaling of semiconductor process technology, the circuit timing is increasingly impacted by process variations. It is thus important to categorize high-speed digital circuits into multiple bins of d...
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With the continual scaling of semiconductor process technology, the circuit timing is increasingly impacted by process variations. It is thus important to categorize high-speed digital circuits into multiple bins of different performances. However, the speed-binning process typically needs very long test application time. In this paper, we proposed a unified architecture, which can accomplish performance grading with a high confidence and short test application time. Moreover, the proposed architecture can be used for on-line circuit failure prediction and detection. Experimental results are presented to validate the proposed architecture.
Data uncertainty appears in many important XML applications. Recent probabilistic XML models represent different dependency correlations of sibling nodes by adding various kinds of distributional nodes, while there do...
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PLSA(Probabilistic Latent Semantic Analysis) is a popular topic modeling technique for exploring document collections. Due to the increasing prevalence of large datasets, there is a need to improve the scalability of ...
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NAND Flash memories have rapidly emerged as a storage class memory such as SSD (Solid State Disk), CF (Compact Flash) Card, SD (Secure Digital Memory) Card. Due to its distinct operation mechanisms, NAND Flash memory ...
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NAND Flash memories have rapidly emerged as a storage class memory such as SSD (Solid State Disk), CF (Compact Flash) Card, SD (Secure Digital Memory) Card. Due to its distinct operation mechanisms, NAND Flash memory suffers from erase/program endurance, data retention and program/read disturbance problems. Specifically, erase and program operation keeps in developing bad blocks during the lifetime of memory chips. Bad blocks are blocks that contain faulty bits but the ECC (Error Correction Code) algorithm cannot correct them. Although wear leveling tries to balance the erase/program operations on different blocks so that all blocks can wear out at a similar pace, new bad blocks still inevitably *** propose an in-field testing technique which takes some pages in a block as predictors. Due to wear out faster than the other pages, the predictors will become bad before the other pages in the block become bad. The further questions are (1) how to detect those wearing fast pages so as to use them as predictors, (2) how many predictors are needed to achieve a satisfactory prediction accuracy, (3) misprediction will result in what negative impact on performance and endurance.
To minimize Rate-Distortion (RD) cost in video coding, RD Optimization (RDO) technique is adopted, which also brings increasingly computational complexity in Motion Estimation (ME), multiple reference selection and mo...
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Chosen-ciphertext security has been well-accepted as a standard security notion for public key encryption. But in a multi-user surrounding, it may not be sufficient, since the adversary may corrupt some users to get t...
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In this paper, a novel concept of multilayer synthesis and a general framework for texture synthesis method are presented. Within this framework, we first decompose the texture into the supposed pattern layer and mate...
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In this paper, a novel concept of multilayer synthesis and a general framework for texture synthesis method are presented. Within this framework, we first decompose the texture into the supposed pattern layer and material layer in the frequency domain by an E-texton extracting algorithm, then manipulate and extend them respectively according to their own personalities, and finally merge the newly synthesized pattern layer and material layer again to generate the final output. Experiment results show that our method not only greatly improves the synthesis quality for those cases that single-layer synthesis cannot handle well but also provides an ability of achieving various special synthesis effects.
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