检索结果-内蒙古大学图书馆

No-go theorem for one-way quantum computing on naturally occurring two-level systems

Physical Review A 2011年第5期83卷 050301(R)-050301(R)页

作者： Jianxin Chen Xie Chen Runyao Duan Zhengfeng Ji Bei Zeng Department of Computer Science and Technology Tsinghua National Laboratory for Information Science and Technology Tsinghua University Beijing China Department of Physics Massachusetts Institute of Technology Cambridge Massachusetts USA Centre for Quantum Computation and Intelligent Systems (QCIS) Faculty of Engineering and Information Technology University of Technology Sydney New South Wales Australia Perimeter Institute for Theoretical Physics Waterloo Ontario Canada State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijing China Institute for Quantum Computing and Department of Combinatorics and Optimization University of Waterloo Waterloo Ontario Canada

The ground states of some many-body quantum systems can serve as resource states for the one-way quantum computing model, achieving the full power of quantum computation. Such resource states are found, for example, in spin-52 and spin-32 systems. It is, of course, desirable to have a natural resource state in a spin-12, that is, qubit system. Here, we give a negative answer to this question for frustration-free systems with two-body interactions. In fact, it is shown to be impossible for any genuinely entangled qubit state to be a nondegenerate ground state of any two-body frustration-free Hamiltonian. What is more, we also prove that every spin-12 frustration-free Hamiltonian with two-body interaction always has a ground state that is a product of single- or two-qubit states. In other words, there cannot be any interesting entanglement features in the ground state of such a qubit Hamiltonian.

关键词： QUANTUM computers QUANTUM theory HAMILTONIAN operator HAMILTONIAN systems PHYSICS

来源：评论

学校读者我要写书评

暂无评论

A resilient on-chip router design through data path salvaging 11

A resilient on-chip router design through data path salvagin...

引用

Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permanent faults such as manufacturing defects, device wear-out, which hinder the correct operations of the entire system. Therefore, effective fault-tolerant techniques are essential to improve the reliability of NoCs. Prior work mainly focuses on introducing redundancies, which can't achieve satisfactory reliability and also involve large hardware overhead, especially for data path components. In this paper, we propose fine-grained data path salvaging techniques by splitting data path components, i.e., links, input buffers and crossbar into slices, instead of introducing redundancies. As long as there is one fault-free slice for each component, the router can be functional. Experimental results show that the proposed solution achieves quite high reliability with graceful performance degradation even under high fault rate.

关键词： Fault tolerant systems Redundancy Pipelines Routing Circuit faults

来源：评论

学校读者我要写书评

暂无评论

Wear rate leveling: Lifetime enhancement of PRAM with endurance variation 11

Wear rate leveling: Lifetime enhancement of PRAM with endura...

引用

Design Automation Conference

作者： Jianbo Dong Lei Zhang Yinhe Han Ying Wang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling.

关键词： Phase change random access memory Writing Programming Degradation Prediction algorithms Systematics Complexity theory

来源：评论

学校读者我要写书评

暂无评论

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip 11

Vertical interconnects squeezing in symmetric 3D mesh Networ...

引用

Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs' utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant TSV footprint with negligible performance overhead.

关键词： Through-silicon vias Three dimensional displays Pipelines Routing Throughput computer architecture System-on-a-chip

来源：评论

学校读者我要写书评

暂无评论

Generating Chinese Named Entity Data from a Parallel Corpus 5

Generating Chinese Named Entity Data from a Parallel Corpus

引用

5th International Joint Conference on Natural Language Processing, IJCNLP 2011

作者： Fu, Ruiji Qin, Bing Liu, Ting Research Center for Social Computing and Information Retrieval MOE-Microsoft Key Laboratory of Natural Language Processing and Speech School of Computer Science and Technology Harbin Institute of Technology Harbin China

ISBN: (纸本)9789744665645

Annotating Named Entity Recognition (NER) training corpora is a costly process but necessary for supervised NER systems. This paper presents an approach to generate large-scale Chinese NER training data from an English-Chinese discourse level aligned parallel corpus. Difficulty of NER is different among languages due to their unique features. For example, the performance of English NER systems is usually higher than the Chinese ones on average. In our method, we first employ a high performance NER system on one side of a bilingual corpus. And then, we project the NE labels to the other side according to the word level alignment. At last, we select high-quality labeled sentences using different strategies and generate an NER training corpus. In our experiments, we generate a Chinese NER corpus with 167,100 sentences through an English-Chinese parallel corpus. The system trained on the automatically generated corpus attains a comparable result with the one trained on the manually-annotated corpus. Further experiments show that the NER performance is significantly improved on two different evaluation sets by using the generated training data as an additional corpus to the manually-labeled data. © 2011 AFNLP

关键词： Natural language processing systems

来源：评论

学校读者我要写书评

暂无评论

JVM virtual method invoking optimization based on CAM table

JVM virtual method invoking optimization based on CAM table

引用

IEEE International Conference on Networking, architecture and Storage

作者： Cai, Songsong Yang, Yongqiang Lin, Chuanwen Liu, Qi Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Dept. of Computer Science and Technology University of Science and Technology of China Hefei China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769545097

In Java programs, it needs to use the information of the method type to resolve the virtual method dynamically, which restricts the performance greatly. Currently, the solution is mainly the technique of inline caching, which can be divided into two categories: monomorphic inline caching and polymorphic inline caching. Because of the simple implementation of monomorphic inline caching, it is more commonly used, but it cannot resolve the problem of frequently seeing different types of objects at one call site. Although polymorphic inline caching can solve this problem, it is costly. This paper presents the CAM hardware table, proposes a virtual method invoking mechanism based on software and hardware co-design. It solves the problem of frequently seeing different types of objects at one call site, and does not introduce additional overhead. The experimental evaluation shows that it improves the cached hit rate from 13.3% to 76.4% and improves 16.2% performance of the virtual test;it improves the performance of SPECjvm98 by 6.4% on average. © 2011 IEEE.

关键词： Virtual reality

来源：评论

学校读者我要写书评

暂无评论

Fast implementation of DGEMM on Fermi GPU

Fast implementation of DGEMM on Fermi GPU

引用

Supercomputing Conference

作者： Guangming Tan Linchuan Li Sean Triechle Everett Phillips Yungang Bao Ninghui Sun Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Nvidia Corporation India

In this paper we present a thorough experience on tuning double-precision matrix-matrix multiplication (DGEM-M) on the Fermi GPU architecture. We choose an optimal algorithm with blocking in both shared memory and registers to satisfy the constraints of the Fermi memory hierarchy. Our optimization strategy is further guided by a performance modeling based on micro-architecture benchmarks. Our optimizations include software pipelining, use of vector memory operations, and instruction scheduling. Our best CUDA algorithm achieves comparable performance with the latest CUBLAS library. We further improve upon this with an implementation in the native machine language, leading to 20% increase in performance. That is, the achieved peak performance (efficiency) is improved from 302Gflop/s (58%) to 362Gflop/s (70%).

关键词： Graphics processing unit Registers Bandwidth Instruction sets Optimization Memory management

来源：评论

学校读者我要写书评

暂无评论

LIR-OSGi: Extends OSGi to support distributed and heterogeneous ubiquitous computing system

LIR-OSGi: Extends OSGi to support distributed and heterogene...

引用

2011 6th International Conference on Pervasive computing and Applications, ICPCA 2011

作者： Liu, Jinzhao Lu, Xiaojuan Wang, Dan Liu, Xin Lu, Yongqiang Chen, Yu Dept. of Computer Science and Technology Beijing University of Technology Beijing China General Hospital PLA Second Artillery China Research Institute of Information Technology Key Laboratory of Pervasive Computing Ministry of Education Beijing China System Software and Software Engineering Group Laboratory of Pervasive Computing Dept. of Computer Science and Technology Beijing 100084 China

ISBN: (纸本)9781457702082

As an emerging portable service platform, OSGi is now taking a more and more important role in Ubiquitous computing environment. As a module management framework, OSGi provides the functions of dynamic loading and unloading software modules at runtime. But its use is limited because it is centralized and single programming language supported. In this paper we present LIR-OSGi, an extended framework of OSGi, which is designed to add the distribution and programming language independence to OSGi. Meanwhile it is easy to use for developers because of the transparence of service invocation and automation of distribution. Not like OSGi which can be applied only on the Java platform, LIR-OSGi makes programs which may be written in different programming languages be able to call each other transparently so that it can be applied in many different platforms such as DotNet Framework and so on. This brings much convenience to the program development in a distributed and heterogeneous environment. © 2011 IEEE.

关键词： Middleware

来源：评论

学校读者我要写书评

暂无评论

Building algorithmically nonstop fault tolerant MPI programs

Building algorithmically nonstop fault tolerant MPI programs

引用

International Conference on High Performance computing

作者： Rui Wang Erlin Yao Mingyu Chen Guangming Tan Pavan Balaji Darius Buntinas State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Mathematics and Computer Science Argonne National Laboratory USA

With the growing scale of high-performance computing (HPC) systems, today and more so tomorrow, faults are a norm rather than an exception. HPC applications typically tolerate fail-stop failures under the stop-and-wait scheme, where even if only one processor fails, the whole system has to stop and wait for the recovery of the corrupted data. It is now a more-or-less accepted fact that the stop-and-wait scheme will not scale to the next generation of HPC systems. Inspired by the previous stop-and-wait algorithm-based fault tolerance (ABFT) recovery technique, we propose in this paper a nonstop fault tolerance scheme at the application level and describe its implementation. When failure occurs during the execution of applications, we do not stop to wait for the recovery of the corrupted node; instead, we replace it with the corresponding redundant node and continue the execution. At the end of execution, the correct solution can be recovered algorithmically at a very low cost. In order to implement the scheme, some new fault-tolerant features of the Message Passing Interface (MPI) have been investigated and utilized in the MPICH implementation of MPI. We also describe a case study using High Performance Linpack (HPL) with these new features and evaluate the performance of both our new scheme and ABFT recovery. Experimental results show the advantage of our new scheme over ABFT recovery even in a small scale.

关键词： Fault tolerant systems Encoding Redundancy Checkpointing Matrix decomposition Libraries

来源：评论

学校读者我要写书评

暂无评论

Computation Pattern Driven Reuse of Manual Optimizations for GPGPUs

Computation Pattern Driven Reuse of Manual Optimizations for...

引用

IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Shixiong Xu Dongni Han Li Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences Beijing China

The wide application of General Purpose Graphic Processing Units (GPGPUs) results in large manual efforts on porting and optimizing algorithms on them. However, most existing automatic ways of generating GPGPU code fail to conduct optimization strategies regarding a specific computation and to reuse constantly evolving manual optimizations. In this paper, we present a computation pattern driven approach for computation-specific GPGPU code generation and optimization, which in turn reuses manual optimizations to a certain extent. We suggest language extensions to OpenMP, high-level data structure attributes, in order to assist the process of computation pattern matching and to help give users intuitive performance tuning parameters in the view of data structure attributes. We illustrate the feasibility of this approach through three important computation dwarfs, which are dense matrix, sparse matrix, and structured mesh computation in scientific computing. We also build a prototype OpenMP-to-CUDA translator that consists of computation pattern recognition and code template instantiation. The experimental results demonstrate the performance benefits of computation pattern driven method. To our best knowledge, it is the first work on reusing manual optimizations for GPGPUs with computation pattern driven approach.

关键词： Data structures Optimization Pattern matching Sparse matrices Manuals Libraries Tuning

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：