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Adaptive discriminant analysis for face recognition from single sample per person

Adaptive discriminant analysis for face recognition from sin...

引用

IEEE International Conference on Automatic Face and Gesture Recognition

作者： Kan, Meina Shan, Shiguang Su, Yu Chen, Xilin Gao, Wen Digital Media Research Center Institute of Computing Technology CAS Beijing China Key Laboratory of Intelligent Information Processing Chinese Academy of Sciences Beijing China Department of Computer Science University of Caen France Institute for Digital Media Peking University Beijing China School of Computer Science and Technology Harbin Institute of Technology Beijing China

ISBN: (纸本)9781424491407

Discriminant analysis, especially Fisherface and its numerous variants, have achieved great success in face recognition. However, these methods fail to work for face recognition from Single Sample per Person (SSPP), since they need more than one sample per person to estimate the within-class scatter matrix. To break this inability of traditional discriminant analysis, our paper proposes Adaptive Discriminant Analysis (ADA). In our method, the within-class scatter matrix of each enrolled subject is estimated from his/her single sample, by inferring from a generic training set with multiple samples per person. The inference is inspired by a simple intuition that similar person follows similar within-class variations. Specifically, both kNN regression and Lasso regression are explored for this purpose. We evaluate our method on FERET database and a large real-world face database. The results are very impressive compared with dominant traditional solutions to SSPP problem. © 2011 IEEE.

关键词： Discriminant analysis

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Online timing variation tolerance for digital integrated circuits

Online timing variation tolerance for digital integrated cir...

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IEEE International Test Conference

作者： Guihai Yan Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Beijing China

Ensuring safe timing increasingly becomes a paramount challenge with the technology scaling to nanoscale. This study aims to provide timing variation detection and tolerance solutions. We first propose a versatile online timing variation detection scheme which can handle multiple types of faults. With the capability of detection, we further propose two tolerance schemes to eliminate runtime margin in DVFS applications and improve lifetime reliability under progressive aging mechanisms, respectively. Lastly, given the more complicated PVT variations whose primary circuit implication is also timing variations, we propose TEA-TM, a novel architectural scheme to reduce timing emergencies. Collectively, we aims to build a comprehensive framework for timing variation tolerance and demonstrate several specific applications.

关键词： Delay Aging Circuit faults Circuit stability Sensors Stability analysis

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A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications

A Fault Criticality Evaluation Framework of Digital Systems ...

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Asian Test Symposium (ATS)

作者： Yuntan Fang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Error tolerance is evolving into a new computing paradigm with further technology scaling, cost constraint, system scalability and emerging applications. Distinguished from defect tolerance and fault tolerance, error tolerance is based on application characteristics and relaxes the constraint of 100 percent functional correctness. From the viewpoint of error tolerance, this paper proposes a framework across multiple layers for fault criticality evaluation. Furthermore, taking an H.264/AVC decoder as an example, fault injection experiments demonstrate that for different functional modules, the faults in them bear different fault criticalities because of their unbalanced effects on applications, the faults in the same module also have diverse fault criticalities. The information that which faults are most critical can aid in test for yield and design for cost-effective fault tolerance. Error control techniques can be used to suppress error propagation and make more faults acceptable.

关键词： Circuit faults Decoding Video sequences Measurement PSNR Fault diagnosis Transform coding

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Web service composition techniques in a health care service platform

Web service composition techniques in a health care service ...

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2011 IEEE 9th International Conference on Web Services, ICWS 2011

作者： Wang, Pengwei Ding, Zhijun Jiang, Changjun Zhou, Mengchu Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States

ISBN: (纸本)9780769544632

The information technology has been recognized as one of the most important means to improve health care and curb its ever-increasing cost. However, existing efforts mainly focus on informatization of hospitals or medical institutions within organizations, and few are directly oriented to individuals. The strong demand for various health services from customers calls for the creation of powerful individual-oriented personalized health care service systems. Web service composition (WSC) and related technologies can greatly help one build such systems. This paper aims to present a newly developed platform called a Public-oriented Health care Information Service Platform (PHISP) and several novel WSC techniques that are used to build it. Among them include WSC techniques that can well support branch and parallel structures. © 2011 IEEE.

关键词： Web services

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Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors

Transparent dynamic binding with fault-tolerant cache cohere...

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International Conference on Dependable Systems and Networks (DSN)

作者： Shuchang Shan Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level fault-tolerant approaches bind two cores to implement redundant execution and error detection. However, along with more cores integrated into one chip, existing static and dynamic binding schemes suffer from the scalability problem when considering the violation effects caused by external write operations. In this paper, we present a transparent dynamic binding (TDB) mechanism to address the issue. Learning from static binding schemes, we involve the private caches to hold identical data blocks, thus we reduce the global masters-lave consistency maintenance to the scale of the private caches. With our fault-tolerant cache coherence protocol, TDB satisfies the objective of private cache consistency, therefore provides excellent scalability and flexibility. Experimental results show that, for a set of parallel workloads, the overall performance of our TDB scheme is very close to that of baseline fault-tolerant systems, outperforming dynamic core coupling by 9.2%, 10.4%, 18% and 37.1% when considering 4, 8, 16 and 32 cores respectively.

关键词： Master-slave Fault tolerance Fault tolerant systems Coherence System-on-a-chip Pipelines

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Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC

Wrapper Chain Design for Testing TSVs Minimization in Circui...

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Asian Test Symposium (ATS)

作者： Yuanqing Cheng Lei Zhang Yinhe Han Jun Liu Xiaowei Li Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing CN

Three dimensional (3D) System-on-Chips (SoCs) that typically employ through-silicon vias (TSVs) as vertical interconnects, emerge as a promising solution to continue Moore's law. Whereas, it also brings challenging problems, one of which is the test wrapper chain design and optimization, especially for circuit-partitioned 3D SoCs in which scan chains can cross among layers. Test time is the primary goal for wrapper chain design, both for 2D and 3D SoCs. The 3D SoC wrapper chain design problem can be converted into the well-studied2D one by projecting wrapper chain components of all layers to one virtual layer. Thereafter, we can leverage 2D optimization algorithms to determine the composition of wrapper chains and thus guarantee minimal testing time for 3D SoCs. One specific thing for circuit-partitioned 3D SoCs is that TSVs are needed to connect cross-layer wrapper structures to form the wrapper chains. As TSVs occupy planar chip area and will aggravate the routing congestion problem, it is necessary to reduce TSVs for test purpose as much as possible. In this work, we observe that by varying the connection orders of wrapper chain components, e.g., scan chains and I/O cells, the TSVs consumed vary significantly. Based on the above, we formulate this problem and propose novel heuristic to tackle it. Experimental results show that the proposed solution can save on average 33.2% amount of TSVs when compared to a prior intuitive method.

关键词： Three dimensional displays System-on-a-chip Through-silicon vias Testing Optimization Algorithm design and analysis

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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

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Attention driven face recognition: A combination of spatial variant fixations and glance

Attention driven face recognition: A combination of spatial ...

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IEEE International Conference on Automatic Face and Gesture Recognition

作者： Wang, Chongxiu Qing, Laiyun Miao, Jun Fang, Fang Chen, Xilin School of Information Science and Engineering Graduate University of Chinese Academy of Sciences Beijing 100049 China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer Science and Technology Harbin Institute of Technology Harbin 150001 China

ISBN: (纸本)9781424491407

This paper proposes a novel face recognition algorithm inspired by the selective attention of Human Visual System (HVS). We record four observers' eye movements when they are viewing 100 FRGC [1] frontal view face images and find that the observers are highly consistent in the regions fixated. Inspired by the fact that fovea of HVS has a much higher spatial acuity than the periphery, a face recognition algorithm based on spatial variant sampling is proposed to simulate such foveated imaging phenomenon, where more information is reserved for the fixated regions. Moreover, information extracted from glance which adopts the low spatial frequency components of the image is integrated into the face recognition system to elicit a percept that occurs before any fixations. The experimental results on FERET database [2] demonstrate that the proposed method not only reduces the computational cost, but also achieves comparable performance, which shows that the characteristics of the HVS provide valuable insights into face recognition. © 2011 IEEE.

关键词： Face recognition

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An ultrasound system for tumor detection in soft tissues using low transient pulse

An ultrasound system for tumor detection in soft tissues usi...

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2011 7th IEEE International Conference on Automation Science and Engineering, CASE 2011

作者： Ratnakar, Ashish R. Zhou, MengChu Dept. of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102-1982 United States MoE Key Laboratory of Embedded System and Service Computing Tongji University Shanghai 200092 China

ISBN: (纸本)9781457717307

This work presents a method to detect the size and location of tumor in soft tissues using ultrasound. Quantitative ultrasound is utilized to allow an ultrasound signal to be sent from a transmitter to multiple receivers. This received signal is analyzed for echogenic and echolucent tumors to differentiate between the two along with non-tumor sample and also studied for the delay to determine the size/location of the tumor. The proposed system utilizes Low Transient Pulse (LTP) technique and is implemented using Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) technologies. In this co-design architecture, DSP carries out the analysis of received demodulated signal at a lower speed while FPGA runs at a higher one to generate LTP signal and demodulate bandpass ultrasonic signal. This work elaborates the implementation of Quadrature Amplitude Modulation (QAM) receiver on FPGA for the received signal from an ultrasound detector. LTP is applied to the tumor samples through the transmitter and the received signal at an ultrasonic receiver is passed through QAM to obtain different maxima that are then further used to compute the location and the size of the tumor using DSP. This dual platform co-design demonstrates a good application of a FPGA/DSP platform for the LTP generation and received signal processing. © 2011 IEEE.

关键词： Tumors

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Roughness in vector spaces

Roughness in vector spaces

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2011 IEEE International Conference on Granular computing, GrC 2011

作者： Wu, Mingfen Xie, Xiangyun Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer Science Wuyi University Guangdong China School of Mathematics and Computational Science Wuyi University China

ISBN: (纸本)9781457703713

Rough set theory proposed by Pawlak, is a complementary generalization of classical set theory. The relations between rough sets and algebraic systems endowed with two binary operations such as rings, groups and semigroups have been already considered. Wu, Xie and Cao defined a pair of rough approximation operators based on a sub-space. In this paper we do the further study about the upper (lower)approximations. We propose concepts of W-upper(lower) rough subspaces in an approximation space and give some properties of the upper(lower) and rough subspaces. Some characterizations of the upper(lower) rough subspace are expressed with addition and intersection operations of subspaces. At the same time, some counterexamples are offered to illustrate the relevant results. © 2011 IEEE.

关键词： Rough set theory

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