MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore ...
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MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in All to all communication. However, many small synchronization messages are required in All to all communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of All to all communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2¡ÌN. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of All to all communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%.
Pulse coupled neural network (PCNN), a wellknown class of neural networks, has original advantage when applied to image processing because of its biological background. However, when PCNN is used, the main problem is ...
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The large-scale data parallelism processing is an inherent characteristic of artificial neural networks, but the networks bring the efficiency problems of data processing. As one of the artificial neural networks, Rad...
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The large-scale data parallelism processing is an inherent characteristic of artificial neural networks, but the networks bring the efficiency problems of data processing. As one of the artificial neural networks, Radial Basis Function (RBF) neural networks have the same problem. Therefore, how to reduce the scale of data to improve the efficiency of data processing has been a hot issue among the artificial intelligence scholars. Based on the traditional RBF neural networks, this paper puts forward a method which determines the important degree of the sample attributes based on knowledge entropy of Rough set by analyzing the relationship between the knowledge entropy and the weight of the sample attributes, and assesses the importance of the sample attributes between the input layer and the hidden layer, namely the attribution reduction, so as to achieve reduce the scale of data processing. The ultimate aim of training RBF neural networks is to seek a set of suitable networks parameters which makes the sample output error achieve the minimum or required accuracy, while Genetic Algorithm (GA) has the properties of finding out the optimal solution through multiplepoint random search in the solution space, so Genetic Algorithm is used to optimize the centers, the widths and the weights between the hidden layer and the output layer of RBF neural networks in training the networks. Finally, a model about A Rough RBF Neural Networks Optimized by the Genetic Algorithm (GA-RS-RBF) is proposed in this paper. The simulation results show that the rough RBF neural network optimized by the Genetic Algorithm is better than the traditional RBF neural networks in classification about Iris datasets.
The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is...
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ISBN:
(纸本)9781457712227
The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is consumed. This paper presents a direct measurement method to measure the power of main computer components with fine time granularity. To achieve this goal, only small amount of extra hardware are employed. An approach to synchronize power dissipation with program phases has also been proposed in this paper. Based on the preliminary version of our tools, we measure the power of CPU, memory and disk when running SPEC CPU2006 benchmarks, and prove that measurement with fine time granularity is essential. The phenomenon we observe from memory power may be served as a guide for memory management or architecture design towards energy efficiency.
Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizin...
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Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.
In this paper, a new visual saliency detection method is proposed based on the spatially weighted dissimilarity. We measured the saliency by integrating three elements as follows: the dissimilarities between image pat...
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As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more perfo...
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As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.
Some wafer fabrication processes are repeated processes, e.g. atomic layer deposition (ALD) process. For such processes, the wafers need to visit some processing modules for a number of times, which complicates the cy...
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Based on analysis of basic cubic spline interpolation, the clamped cubic spline interpolation is generalized in this paper. The methods are presented on the condition that the first derivative and second derivative of...
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The rough neural networks (RNNs) are the neural networks based on rough set and one kind of hot research in the artificial intelligence in recent years, which synthesize the advantage of rough set to process uncertain...
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