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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

关键词： Network-on-a-chip Delay Prototypes Network topology Throughput Routing System-on-a-chip Communication system traffic control computer architecture Memory

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A stochastic method for controlling the scaling parameters of Cauchy mutation in fast evolutionary programming

A stochastic method for controlling the scaling parameters o...

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Congress on Evolutionary Computation

作者： Yunji Chen Ke Tang Tianshi Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Nature Inspired Computation and Applications Laboratory Department of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling parameter of the Cauchy mutation is invariable, which has become an obstacle for FEP to reach better performance. This paper proposes and analyzes a new stochastic method for controlling the variable scaling parameters of Cauchy mutation. This stochastic method collects information from a group of individuals randomly selected from the population. Empirical evidence validates our method to be very helpful in promoting the performance of FEP.

关键词： Stochastic processes Genetic mutations Genetic programming Laboratories Random variables Gaussian distribution Control systems Stochastic systems computer architecture computer applications

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architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File

Architecture Level Energy Modeling and Optimization for Mult...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Ge Zhang Xu Yang Yiwei Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Information and Technology University of International Relations UIR Beijing China

In modern high performance microprocessors, multi-ported register-files are commonly used and critical in both performance and energy consumption. As capability and issue width of register-file grows, its energy consumption increases rapidly. Much prior work about energy-efficient register-file design is focusing on various low levels except for architecture level. In this paper, an accurate architectural level energy model for register-file is proposed and verified, based on which some efficient and practical improvements are presented to save energy without changing the internal circuits or structure of register-file. We implemented a full-customized 64-bit width 64-entry depth physical register-file with 8 read ports and 4 write ports, whose power is as low as 20 mW, in a 1 GHz 4-issue out-of-order 64-bit MIPS microprocessor, Godson-2 [1], using 90 nm CMOS process. 56.0% of reading energy and 20.3% of writing energy can be saved.

关键词： Circuits computer architecture Energy consumption Microprocessors Registers Energy efficiency Out of order CMOS process Writing Semiconductor device modeling

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A Highly Efficient Inter-domain Communication Channel

A Highly Efficient Inter-domain Communication Channel

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International Conference on computer and Information technology (CIT)

作者： Hongyong Zang Kuiyan Gu Yaqiong Li Yuzhong Sun Dan Meng Chinese Academy of Sciences Beijing China Institute of Computing Technology Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Dongxin Geology Research Institute of Shengli Oilfield Dongying Shandong China

With virtual machine technology, distributed services deployed in multiple cooperative virtual machines, such as multi-tier Web services, may reside on one physical machine. This situation requires an efficient inter-domain communication channel, and meanwhile transparency and security should be guaranteed, for diverse existing distributed applications are serving on plenty of machines. In this paper, we have implemented a highly efficient inter-domain communication channel, called SChannel, with full transparency to both user applications and network protocol stack, and security between guest domains on Xen platform. Between two co-resident domains, SChannel establishes a two-way shared memory channel with elastic size, which is set up using static shared memory mechanism, instead of high-cost dynamic shared memory. Furthermore, SChannel avoids one additional copy from the shared data channel on the receiver domain side. In our evaluation using a number of standard benchmarks, SChannel increases the throughput 5 times than standard inter-domain mechanism offered by the hypervisor. Compared with other typical transparent inter-domain communication mechanism, SChannel achieves approximately 44.5% improvement of throughput, and reduces more than 3500 CPU cycles per packet.

关键词： Communication channels Virtual machine monitors Virtual machining Protocols Throughput Hardware Data security Costs Distributed computing Physics computing

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An immune based algorithm for Chinese network short text clustering

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Zidonghua Xuebao/ Acta Automatica Sinica 2009年第7期35卷 896-902页

作者： He, Tao Cao, Xian-Bin Tan, Hui School of Computer Science and Technology University of Science and Technology of China Hefei 230027 China Key Laboratory of Software in Computing and Communication Anhui Province Hefei 230027 China School of Computer Science and Technology Harbin Institute of Technology Harbin 150001 China

Network short text clustering is a major technology in network content security. Since Chinese network short text is less of keywords and full of anomalous writings, the traditional text clustering method is not directly suitable for network short text clustering. This paper presents an immune network regulation based method to cluster Chinese network short texts. First, Chinese N-gram chunks are extracted and transformed to Chinese pinyin to form the feature representation to each Chinese network short text, so as to relieve these two characteristics' bad influence on the clustering performance. Then, the network short text set is constructed as a dynamic network and an immune network learning mechanism is used to learn the similarity among short texts and therefore to gain a better clustering result. Experiments show our method can get better performance in Chinese network short text clustering, compared with traditional method such as K-means. © 2009 Acta Automatica Sinica. All rights reserved.

关键词： Cluster analysis

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Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs 09

Detecting and Eliminating Potential Violations of Sequential...

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International Symposium on Code Generation and Optimization (CGO)

作者： Yuelu Duan Xiaobing Feng Lei Wang Chao Zhang Pen-Chung Yew Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Computer Science and Engineering University of Minnesota Twin-Cities Minneapolis USA

ISBN: (纸本)9780769535760

When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n 2 ), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.

关键词： Programming profession Delay Set theory computer bugs Performance loss Chaos computer science Laboratories Concurrent computing computer architecture

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Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Extended Selective Encoding of Scan Slices for Reducing Test...

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Asian Test Symposium (ATS)

作者： Jun Liu Yinhe Han Xiaowei Li School of Computer and Information Hefei University of Technology Hefei China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding.

关键词： Encoding Circuit testing Memory Test data compression Filling Laboratories computer architecture Merging Hardware System testing

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Dynamic assembly classification algorithm for short text

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Tien Tzu Hsueh Pao/Acta Electronica Sinica 2009年第5期37卷 1019-1024页

作者： Yan, Rui Cao, Xian-Bin Li, Kai Department of Computer Science and Technology University of Science and Technology of China Hefei 230027 China Key Laboratory of Software in Computing and Communication Hefei 230027 China Institute of Technical Security PLA Beijing 100091 China

Short text classification is a key technology in network content security application. However, the sparse features and unbalanced data of the short text make the traditional text classification method incompetent for short text classification. This paper proposed a dynamic assembly classification method for short text classification. In this method, a treelike assembly classifier was constructed to support the classification, which reduced the impact of the sparse features and unbalanced data of the short texts. Further, a dynamic adjusting strategy was presented in the construction procedure, which adjusted the combinational structure of the classifier in an adaptive way. The experimental results show that, comparing with the traditional classifiers such as single classifier and ensemble classifier, the proposed assembly classifier gets better precision rate and recall rate.

关键词： Adaptive boosting

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Research on answer extraction method for domain question answering system(QA)

Research on answer extraction method for domain question ans...

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2009 International Conference on Computational Intelligence and Security, CIS 2009

作者： Mao, Cun-Li Li, Li-Na Yu, Zheng-Tao Han, Lu Guo, Jian-Yi Lei, Xiong-Li School of Information Engineering and Automation Kunming University of Science and Technology Kunming 650051 China Institute of Intelligent Information Processing Computer Technology Application Key Laboratory of Yunnan Province Kunming 650051 China School of Computer Science and Technology Kunming College of Metallurgy Kunming 650093 China School of Architecture and Arts Kunming College of Metallurgy Kunming 650093 China

ISBN: (纸本)9780769539317

The domain knowledge has a direct impact on the result of question - answering (Q & A) in the restricted domain Question Answering System (QA). In this paper, a method of answer extraction for domain Chinese question-and-answer (Q&A) is proposed, which based on the analysis of interrogative sentence and the answer type, carrying on the text retrieval with the help of the domain knowledge and obtaining the relevant paragraphs of the question as the candidate answer. For the question of numeral or list entity type, extracted the question center related domain entity as the answers by adopting the naming entity recognition. For the definition questions, the sentences or paragraphs with higher relevance can be extracted to become the answer based on the relevance ranking between the candidate sentences or paragraphs and questions by combined the computing method of keywords weighting and the method of semantic similarity between the sentences and questions. Experimented on the answer extraction in Yunnan tourism domain, the results show that more remarkable effects have been achieved by adopting the method of answer extraction from domain Chinese question-and-answer. © 2009 IEEE.

关键词： Domain Knowledge

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HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

HPP-Controller: An intra-node controller designed for connec...

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IEEE International Conference on Cluster computing

作者： Qiang Li Panyong Zhang Ninghui Sun Chinese Academy and Sciences China Chinese Academy of Sciences Beijing Beijing CN National Research Center of Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.

关键词： Joining processes Central Processing Unit Delay Bandwidth Supercomputers Petascale computing Control systems Field programmable gate arrays Access protocols Sun

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