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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Xiaochun, Ye Dongrui, Fan Wei, Lin Key Lab of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Exact pairwise sequence alignment algorithms using dynamic programming require quadratic space and time, and this makes these algorithms impractical for large-scale sequences. In this paper, we propose and evaluate a new Anti-Diagonal based Parallel Linear-Space Algorithm (AD-PLSA). It records similarity matrix scores and start points on special anti-diagonals instead of special rows or columns. This algorithm is able to further reduce the total amount of re-computation. It also produces balanced sub-problems with approximately even size, and this is of great benefit to the parallelization. In addition, we establish a dynamic parallelization framework for the efficient acceleration on a symmetric multiprocessor (SMP) platform. The experimental results present liner speedup for long real DNA sequences. Compared with the typical row-col algorithm, our method is able to save more than 30% of the re-computation, and run twice as fast in the backward phase. © 2009 IEEE.

关键词： DNA sequences

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Improved meet-in-the-middle attacks on 7-round AES-192 and 8-round AES-256

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Tongxin Xuebao/Journal on Communications 2010年第9 A期31卷 197-201页

作者： Dong, Xiao-Li Hu, Yu-Pu Chen, Jie Li, Shun-Bo Yang, Yang Key Laboratory of Computer Networks and Information Security of Ministry of Education Xidian University Xi'an 710071 China State Key Laboratory of Information Security Institute of Software Chinese Academy of Sciences Beijing 100049 China School of Science Xi'an University of Architecture and Technology Xi'an 710055 China

A new variant of 5-round distinguisher of meet-in-the-middle attack on AES was constructed by exploiting the properties of the round transform of AES. Based on the variant of distinguisher, meet-in-the-middle attacks on 7-round AES-192 and 8-round AES-256 were presented by using the time-memory tradeoff approach. It is shown that the new results are better than the cryptanalytic results presented at FSE2008 on reduced AES in terms of the time complexity and the memory complexity.

关键词： Cryptography

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A low overhead on-chip path delay measurement circuit

A low overhead on-chip path delay measurement circuit

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18th Asian Test Symposium, ATS 2009

作者： Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China

ISBN: (纸本)9780769538648

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy. © 2009 IEEE.

关键词： Timing circuits

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A scalable scan architecture for Godson-3 multicore microprocessor

A scalable scan architecture for Godson-3 multicore micropro...

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18th Asian Test Symposium, ATS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Wang, Da Han, Yinhe Li, Huawei Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences GUCAS Beijing China

ISBN: (纸本)9780769538648

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores. © 2009 IEEE.

关键词： Comparators (optical)

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M-IVC: Using multiple input vectors to minimize aging-induced delay

M-IVC: Using multiple input vectors to minimize aging-induce...

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18th Asian Test Symposium, ATS 2009

作者： Jin, Song Han, Yinhe Zhang, Lei Li, Huawei Li, Xiaowei Yan, Guihai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China

ISBN: (纸本)9780769538648

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors. © 2009 IEEE.

关键词： Negative bias temperature instability

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A low-complexity synchronization based cache coherence solution for many cores

A low-complexity synchronization based cache coherence solut...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Lin, Wei Fan, DongRui Huang, He Yuan, Nan Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the "flag". We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included. © 2009 IEEE.

关键词： Synchronization

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Multi-tiered on-demand resource scheduling for VM-based data center 09

Multi-tiered on-demand resource scheduling for VM-based data...

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2009 9th IEEE/ACM International Symposium on Cluster computing and the Grid, CCGRID 2009

作者： Song, Ying Wang, Hui Yaqiong, Li Feng, Binquan Sun, Yuzhong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769536224

The trend of using virtualization for server consolidation is more and more popular in enterprise data center. However, ondemand resource allocation among the concurrent hosted services in such a virtualized environment is still a challenge. In order to optimize resource allocation among services in data center, this paper proposes a multi-tiered resource scheduling scheme which automatically provides on-demand capacities to the hosted services via resources flowing among VMs. We model the resource flowing using optimization theory. Based on this model, we present a global resource flowing algorithm in the multi-tiered resource scheduling scheme. This algorithm preferentially ensures performance of some critical services by degrading of others to some extent when resource competition arises. Using our RAINBOW prototype, we evaluate the multitiered resource scheduling scheme with the performance improvements for the most critical services up to 9%˜16%, which are 75% of the maximum improvement margin, while performance degradation of others is up to 2%, and leads to 1%˜5% improvements in resource utilization than RAINBOW without resource flowing. Compared with the existent scheme, our work leads to 9% less improvements for critical services, while introduces 39% less degradation to low priority services. © 2009 IEEE.

关键词： Resource allocation

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Design of new hash mapping functions

Design of new hash mapping functions

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 IEEE.

关键词： Hash functions

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A unified online fault detection scheme via checking of stability violation 09

A unified online fault detection scheme via checking of stab...

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2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09

作者： Guihai, Yan Yinhe, Han Xiaowei, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783981080155

In ultra-deep submicro technology, two of the paramount reliability concerns are soft errors and device aging. Although intensive studies have been done to face the two challenges, most take them separately so far, thereby failing to reach better performance-cost tradeoffs. To support a more efficient design tradeoff, we present a new fault model, Stability Violation, derived from analysis of signal behavior. Furthermore, we propose a unified fault detection scheme - Stability Violation based Fault Detection (SVFD), by which the soft errors (both Single Event Upset and Single Event Transient), aging delay, and delay faults can be uniformly handled. SVFD can greatly facilitate soft error-resistant and aging-aware designs. SVFD is validated by conducting a set of intensive Hspice simulations targeting 65nm CMOS technology. Experimental results show that SVFD has more robust capability for fault detection than previous schemes at comparable overhead in terms of area, power, and performance. © 2009 EDAA.

关键词： Fault detection

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

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18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

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