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检索条件"机构=Key Laboratory of Computer Architecture Institute of Computing Technology"
3526 条 记 录,以下是3271-3280 订阅
Online computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures
Online Computing and Predicting Architectural Vulnerability ...
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Pacific Rim International Symposium on Dependable computing
作者: Songjun Pan Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft error tolerance techniques (such as redundant multithreading and instruction duplication) can achieve high fault coverage but at t... 详细信息
来源: 评论
Utility analysis for Internet-oriented server consolidation in VM-based data centers
Utility analysis for Internet-oriented server consolidation ...
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IEEE International Conference on Cluster computing
作者: Ying Song Yanwei Zhang Yuzhong Sun Weisong Shi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Wayne State University Detroit USA
Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in today's Internet-service-oriented enter... 详细信息
来源: 评论
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
Variation-Aware Scheduling for Chip Multiprocessors with Thr...
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Pacific Rim International Symposium on Dependable computing
作者: Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration... 详细信息
来源: 评论
Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan
Flip-Flop Selection for Transition Test Pattern Reduction Us...
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Pacific Rim International Symposium on Dependable computing
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (... 详细信息
来源: 评论
Design of New Hash Mapping Functions
Design of New Hash Mapping Functions
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International Conference on computer and Information technology (CIT)
作者: Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much confli... 详细信息
来源: 评论
Evaluation Method of Synchronization for Shared-Memory On-Chip Many-Core Processor
Evaluation Method of Synchronization for Shared-Memory On-Ch...
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International Symposium on Parallel and Distributed Processing with Applications, ISPA
作者: Fenglong Song Zhiyong Liu Dongrui Fan He Huang Nan Yuan Lei Yu Junchao Zhang Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
On-chip many core architecture is an emerging and promising computation platform. High speed on-chip communication and abundant chipped resources are two outstanding advantages of this architecture, which provide an o... 详细信息
来源: 评论
Study on Fine-Grained Synchronization in Many-Core architecture
Study on Fine-Grained Synchronization in Many-Core Architect...
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ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)
作者: Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained syn... 详细信息
来源: 评论
Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor
Data Management: The Spirit to Pursuit Peak Performance on M...
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International Symposium on Parallel and Distributed Processing with Applications, ISPA
作者: Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN
To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especia... 详细信息
来源: 评论
A case study of improving at-speed testing coverage of a gigahertz microprocessor
A case study of improving at-speed testing coverage of a gig...
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IEEE International Conference on Electronics, Circuits and Systems (ICECS)
作者: Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This pape... 详细信息
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A stochastic method for controlling the scaling parameters of Cauchy mutation in fast evolutionary programming
A stochastic method for controlling the scaling parameters o...
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Congress on Evolutionary Computation
作者: Yunji Chen Ke Tang Tianshi Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Nature Inspired Computation and Applications Laboratory Department of Computer Science and Technology University of Science and Technology of China Hefei Anhui China
The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling pa... 详细信息
来源: 评论