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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

Asia and South Pacific Design Automation Conference

作者： Fei Wang Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

关键词： Circuit faults Combinational circuits Fault diagnosis Design for disassembly Circuit testing Software testing Signal processing Flip-flops Logic Laboratories

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A Scan-Based Delay Test Method for Reduction of Overtesting

A Scan-Based Delay Test Method for Reduction of Overtesting

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Hui Liu Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.

关键词： Delay Circuit testing Sequential analysis Clocks Circuit faults Automatic test pattern generation Sequential circuits Power dissipation Electrical fault detection Fault detection

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A Network Memory architecture Model and Performance Analysis

A Network Memory Architecture Model and Performance Analysis

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International Conference on Networking, architecture, and Storage (NAS)

作者： Li Liu Mingyu Chen Yungang Bao Jianwei Xu Jianping Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

This paper presents a network memory architecture and makes a performance model to analysis the slowdown caused by the remote access delay. In this architecture the network memory is accessed through a smart network memory controller. A local page cache and a virtual page prefetching engine are designed in the smart network memory controller to improve the memory access performance.

关键词： Prefetching Delay Memory architecture Memory management computer architecture Engines Monitoring

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Automatic Implementation of Multi-partitioning Using Global Tiling

Automatic Implementation of Multi-partitioning Using Global ...

引用

International Conference on Parallel and Distributed Systems (ICPADS)

作者： Lei Liu Dingfei Zhang Hengjie Li Li Chen Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Strategies for partitioning an application¿s data and computation play fundamental role in determining the efficiency of parallelization. This paper describes a sophisticated strategy for partitioning data and computation known as multi-partitioning, which can support the best parallelization for some applications such as the line sweep computations. However, the implementation of multi-partitioning is very difficult and, as we know, there is none automatic parallelizing compiler supports such partitioning strategy. Though the dHPF compiler implemented multi-partitioning as a special extension for block style HPF partitioning, it still needs the programmer¿s participation to analyze the application and decide the data distribution scheme. In this paper, we present a global tiling transformation algorithm and a tile-to-processors mapping strategy called hyper-diagonal modular mapping, to implement the multi-partitioning strategy. The experimentation with NPB2.3-serial SP shows that the code generated by the compiler achieves scalable performance.

关键词： Concurrent computing Distributed computing computer applications Program processors Partitioning algorithms Tiles Laboratories computer architecture Partial differential equations Navier-Stokes equations

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Robust test generation for power supply noise induced path delay faults

Robust test generation for power supply noise induced path d...

引用

Asia and South Pacific Design Automation Conference

作者： Xiang Fu Huawei Li Yu Hu Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424419210

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.

关键词： Noise robustness Power generation Power supplies Noise generators Delay Circuit testing Circuit faults Timing Switches Feeds

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Static Crosstalk Noise Analysis with Transition Map

Static Crosstalk Noise Analysis with Transition Map

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Minjin Zhang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size scales into the nanometer era, crosstalk noise begins to exert a more significant adverse influence on circuit and need to be estimated efficiently in the design process. This paper proposes a novel static crosstalk noise analysis method to quickly and accurately calculate the propagation and combination of glitch noise in circuit. The key of this approach, namely transition map, is a bitmap structure which records the possible arrival times of a line. Based on it, this approach can cope with multiple coupling effects using the timing information of circuit. The analytical results for seven largest ISCAS89 benchmark circuits show that the proposed technique is highly effective in reducing the number of reported false noise violations.

关键词： Crosstalk Circuit noise Timing Noise reduction Noise figure Phase noise Information analysis Electronic equipment testing Circuit testing System testing

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Building Ezceptions with XML

Building Ezceptions with XML

引用

2008全国软件与应用学术会议(NASAC'08)

作者： YUE Qiang LU Xiao-yi ZHA Li Key Laboratory of Computer Network Institute of Computing Technology ChineseAcademy of Sciences Beijing 100190 China

In order to support XML-based exception definition with development for Web Services, we adopted XML to describe an exception and the handler. Since Service-oriented architecture involves many layered and interrelated technologies which can be used to design and build Web Services, the technology that we consider here is a uniform,language-neutral format for the exception design, called XML syntax for exception descriptions (x2d). This paper outlines our representing approach to x2d for Web Services, and summarizes implementation issues with this strategy.

关键词： Web Services Ezception design Definition space Section User-defined handler

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Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects

Deterministic Diagnostic Pattern Generation (DDPG) for Compo...

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IEEE International Test Conference

作者： Fei Wang Hu Yu Huawei Li Xiaowei Li Jing Ye Huang Yu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China. huyu@*** Mentor Graphics Corporation 300 Nickerson Rd. Marlborough MA 01752 USA.

Scan chain failure diagnosis has become an important means for silicon debug and yield improvement. Although plenty of prior work discussed how to perform scan chain diagnosis, most of the previously proposed techniques made an assumption that the system logic is fault-free, which could be an impractical assumption leading to incorrect diagnostic results. In this paper, we propose a scan chain deterministic diagnostic pattern generation (DDPG) method that can tolerate the faults in the system logic without degradation of chain diagnostic resolution and precision. The entire flow includes three steps. In the first step, patterns are created to propagate the state of a targeted scan cell to as many reliable observation points as possible. In the second step, the load error probability of each targeted scan cell is calculated based on the hamming distances between the observed responses and the expected good or faulty responses. In the last step, a suspect profile is plotted, which can be used to identify the suspect scan cell(s) based on ranking scores. Experimental results show that the diagnostic resolution and precision are not degraded even with dozens of faults injected into the system logic.

关键词： Fault diagnosis Degradation Hardware Logic testing Laboratories computer architecture computer graphics Silicon Error probability Logic design

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A novel fuzzy likelihood measure algorithm

A novel fuzzy likelihood measure algorithm

引用

International Conference on computer Science and Software Engineering, CSSE 2008

作者： Ding, Shifei Jin, Fengxiang School of Computer Science and Technology China University of Mining and Technology Xuzhou 221008 China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Science Beijing 100080 China College of Geoinformation Science and Engineering Shandong University of Science and Technology Qingdao 266510 China

ISBN: (纸本)9780769533360

Similarity Measure(PSM) is a kind of measurement that measure the size of similarity between two patterns, it plays a key role in the analysis and research of pattern recognition, machine learning, clustering analysis. This article will firstly study the current PSM theory, point out its application range;secondly, discuss the axiomatic theory of fuzzy likelihood measure, give the frequently-used algorithms of fuzzy likelihood measure that based on axiomatic theory;finally, advance a new kind of fuzzy likelihood function, then establish the Fuzzy Likelihood Measure(FLM) between two fuzzy sets, so as to describe the similar degree between two fuzzy sets. FLM theory not only enriches and improves the PLS theory, and also provides new research methods for the theory research such as pattern recognition, machine learning, clustering analysis and so on. © 2008 IEEE.

关键词： Fuzzy sets

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Kernel Parameter Optimization for Kernel-based LDA methods

Kernel Parameter Optimization for Kernel-based LDA methods

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International Joint Conference on Neural Networks

作者： Huang, Jian Chen, Xiaoming Yuen, P. C. Zhang, Jun Chen, W. S. Lai, J. H. School of Information Science and Technology Sun Yat-Sen University China Guangdong Key Laboratory of Information Security China Department of Computer Science Hong Kong Baptist University Institute of Computing Science College of Mathematics and Computational Science Shenzhen University China

ISBN: (纸本)9781424418206

Kernel approach has been employed to solve classification problem with complex distribution by mapping the input space to higher dimensional feature space. However, one of the crucial factors in the Kernel approach is the choosing of kernel parameters which highly affect the performance and stability of the kernel-based learning methods. In view of this limitation, this paper adopts the Eigenvalue Stability Bounded Margin Maximization (ESBMM) algorithm to automatically tune the multiple kernel parameters for Kernel-based LDA methods. To demonstrate its effectiveness, the ESBMM algorithm has been extended and applied on two existing kernel-based LDA methods. Experimental results show that after applying the ESBMM algorithm the performance of these two methods are both improved.

关键词： Kernel Fisher Discriminant Kernel Parameter Stability Face Recognition

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