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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

引用

Asia and South Pacific Design Automation Conference

作者： Yu Hu Xiang Fu Xiaoxin Fan Hideo Fujiwara Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate School of Information Science Nara Institute of Science and Technology Ikoma Nara Japan

ISBN: (纸本)9781424419210

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.

关键词： Routing Flip-flops Circuit testing Power dissipation Read-write memory Wires Random access memory Circuit synthesis Signal synthesis Design for testability

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Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor

Fetching Primary and Redundant Instructions in Turn for a Fa...

引用

Pacific Rim International Symposium on Dependable computing

作者： Shijian Zhang Weiwu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor¿s instruction fetch bandwidth on a program¿s performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor.

关键词： Fault tolerance Microprocessors Delay Hardware Costs Bandwidth Fault detection Performance analysis Degradation Accuracy

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VEAL: Virtualized Execution Accelerator for Loops

VEAL: Virtualized Execution Accelerator for Loops

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Annual International Symposium on computer architecture, ISCA

作者： Nathan Clark Amir Hormati Scott Mahlke College of Computing Georgia Institute of Technology USA Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunction with general purpose processors to achieve future performance goals. There is a serious drawback to accelerators, though: binary compatibility. An application compiled to utilize an accelerator cannot run on a processor without that accelerator, and applications that do not utilize an accelerator will never use it. To overcome this problem, we propose decoupling the instruction set architecture from the underlying accelerators. Computation to be accelerated is expressed using a processorpsilas baseline instruction set, and light-weight dynamic translation maps the representation to whatever accelerators are available in the system. In this paper, we describe the changes to a compilation framework and processor system needed to support this abstraction for an important set of accelerator designs that support innermost loops. In this analysis, we investigate the dynamic overheads associated with abstraction as well as the static/dynamic tradeoffs to improve the dynamic mapping of loop-nests. As part of the exploration, we also provide a quantitative analysis of the hardware characteristics of effective loop accelerators. We conclude that using a hybrid static-dynamic compilation approach to map computation on to loop-level accelerators is an practical way to increase computation efficiency, without the overheads associated with instruction set modification.

关键词： Hardware Application software Costs computer architecture Acceleration Algorithm design and analysis computer aided instruction Application specific integrated circuits Energy consumption Multicore processing

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Instruction level test for parallel multipliers

Instruction level test for parallel multipliers

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15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

作者： Lin, Ma. Yan, Gao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100190 China College of Electronics and Information Engineering Tongji University SiPing Road 1239 Shanghai 200092 China Graduate University of Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers © 2008 IEEE.

关键词： System-on-chip

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing System testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

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Convergence property analysis for PSO based on cluster-degree

Convergence property analysis for PSO based on cluster-degre...

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2008 International Conference on Computational Intelligence and Security, CIS 2008

作者： Quansheng, Dou Zhijun, Yu Ping, Jiang Zhongzhi, Shi Yantai Dongfang Electronics Information Industry Group Co. Ltd. Yantai China School of Nursing Binzhou Medical University Yantai China School of Computer Science and Technology Shandong Institute of Business and Technology Yantai China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769535081

The concept of cluster-degree was put forward and distribute status of particle with different clusterdegree was studied. The reasonable parameters setting range based on cluster-degree was proposed. Under the direction of cluster-degree, many parameters which can get better searching results were found. So this paper is helpful for the choosing and adjustment of PSO parameters in practical application. © 2008 IEEE.

关键词： Convergence Computational intelligence computer security Information security Information analysis Industrial electronics computer industry Electronics industry Medical services computer science

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A HyperTransport-based personal parallel computer

A HyperTransport-based personal parallel computer

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IEEE International Conference on Cluster computing

作者： Xiaojun Yang Fei Chen Hailiang Cheng Ninghui Sun Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Instead of all using commodity components, an approach building a personal parallel computer on top of a non-coherent HyperTransport (HT) fabric is presented in the paper. The advantage is to provide both lower cost and higher performance compared with the existing method. A HT switch is designed and implemented for the interconnection of a set of AMD Opteron processors for building an in-a-box cluster. On our prototyping system, the result of evaluation experiments shows this approach gives the better performance.

关键词： Switches Program processors computers Bandwidth Fabrics Protocols computer architecture

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A novel hint-based I/O mechanism for centralized file server of cluster

A novel hint-based I/O mechanism for centralized file server...

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IEEE International Conference on Cluster computing

作者： Huan Chen Jin Xiong Ninghui Sun Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer Architecture and System Chinese Academy and Sciences Beijing China

In the medium and small cluster systems, the centralized file server such as NFS is the main approach to provide the storage service with low cost and easy management. However, when multiple parallel applications access the shared storage at the same time, the I/O performance decreases much because of the interference of the I/O requests coming from the different clients. In this paper, a hint-based I/O mechanism is proposed and implemented in the United-FS. By analyzing the hint information of the I/O requests, the related requests are grouped, sorted and scheduled by our hint-based I/O scheduler. The experiments show that our hint-based I/O mechanism nearly doubles the read performance compared with NFS, and has better scalability.

关键词： File systems Servers File servers Performance evaluation Bandwidth Scalability Time factors

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Hierarchical background subtraction using local pixel clustering

Hierarchical background subtraction using local pixel cluste...

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作者： Zhong, Bineng Yao, Hongxun Shan, Shiguang Chen, Xilin Gao, Wen Department of Computer Science and Engineering Harbin Institute of Technology China Digital Media Research Center Institute of Computing Tech. CAS Beijing China Key Laboratory of Intelligent Information Processing CAS Beijing China Digital Media Institute Peking University Beijing China

ISBN: (纸本)9781424421756

We propose a robust hierarchical background subtraction technique which takes the spatial relations of neighboring pixels in a local region into account to detect objects in difficult conditions. Our algorithm combines a per-pixel with a per-region background model in a hierarchical manner, which accentuates the advantages of each. This is a natural combination because the two models have complementary strengths. The per-pixel background model is achieved by mixture of Gaussians Models (GMM) with RGB feature. Although precisely describing background change in high resolution, it suffers from the sensitivity to quick variations in dynamic environment. To tolerate these quick variations, we further develop a novel GMM based per-region background model, which is updated by the cluster centers obtained from a k-means clustering of the pixels' RGB feature in the region. Numerical and qualitative experimental results on challenging videos demonstrate the robustness of the proposed method. © 2008 IEEE.

关键词： Pixels

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Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Observation Point Oriented Deterministic Diagnosis Pattern G...

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Asian Test Symposium (ATS)

作者： Fei Wang Yu Hu Yu Huang Jing Ye Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Mentor Graphics Corporation Marlborough MA USA

Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior work, the proposed new DDPG method directly targets as many observation points as possible to observe the loading error occurred on the targeted scan cell. Experimental results on ISCASpsila89 benchmark circuits show that the proposed DDPG method improves the effectiveness and efficiency of diagnosing compound defects, compared to our prior research.

关键词： Fault diagnosis System testing Circuit faults Hardware Test pattern generators Laboratories computer architecture computer graphics Logic design Timing

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