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IEEE International Conference on Field-Programmable technology (FPT)

作者： Xianyang Jiang Xiaomin Li Yue Tian Kai Wang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Chinese Academy of Sciences China

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

关键词： Acceleration Hardware Field programmable gate arrays Programmable logic arrays Time to market Network interfaces Control systems Supercomputers computer interfaces computer networks

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Bug analysis and corresponding error models in real designs

Bug analysis and corresponding error models in real designs

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IEEE International High-Level Design Validation and Test Workshop

作者： Tao Lv Tong Xu Yang Zhao Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Microprocessor Center Department of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.

关键词： Error analysis computer bugs Microprocessors Circuit faults computer errors computer architecture Circuit testing Automatic test pattern generation Genetic mutations Laboratories

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Shape Analysis of Volume Models by Euclidean Distance Transform and Moment Invariants

Shape Analysis of Volume Models by Euclidean Distance Transf...

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10th IEEE International Conference on computer Aided Design and computer Graphics(第十届CAO/Graphics国际会议)

作者： Dong Xu Hua Li Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese

In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.

关键词： Shape Euclidean distance Skeleton Principal component analysis Laboratories Image converters Data mining Computed tomography Clouds Iterative closest point algorithm

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Hierarchical fault tolerance memory architecture with 3-dimension interconnect

Hierarchical fault tolerance memory architecture with 3-dime...

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IEEE Region 10 International Conference TENCON

作者： Da Wang Yuanjiang Xie Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granularity redundancies and how to combine error correction code (ECC), built-in self-test (BIST), built-in repair-analysis (BIRA), and built-in self-repair (BISR) capabilities. Simulation is employed to estimate the memory behavior of various configurations, and experimental results indicate that the proposed method has substantial reliability improvements over conventional techniques. For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead. It proves the availability of the proposed architecture.

关键词： Fault tolerance Memory architecture Integrated circuit interconnections Error correction codes Integrated circuit reliability Logic circuits Built-in self-test Moore's Law CMOS technology Integrated circuit technology

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Helix Scan: A Scan Design for Diagnosis

Helix Scan: A Scan Design for Diagnosis

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第十二届全国容错计算学术会议

作者： WANG Fei HU Yu LI Xiaowei Graduate School of Chinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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Distributed application integration based on agent grid intelligent platform

Distributed application integration based on agent grid inte...

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2nd International Conference on Innovative computing, Information and Control, ICICIC 2007

作者： Wang, Maoguang Shi, Zhongzhi Luo, Jiewen Zeng, Li School of Computer Science and Technology China University of Mining and Technology Xuzhou 221226 China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate School Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)0769528821

Due to the existence of a large amount of legacy information systems, how to obtain the information and integrate the legacy systems is becoming more and more concerned. This paper introduces the integration pattern based on agent grid. And we propose an agent grid intelligent platform called AGrIP, which can erase information islands and integrate external systems efficiently by encapsulating the distributed application system to agents. AGrIP adopts distributed hierarchical structure, which is capable of integrating external systems to provide the users various services dynamically. AGrIP has proved itself scalable and efficient during the industry projects development and application. © 2007 IEEE.

关键词： Intelligent agents

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3-D projective moment invariants

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Journal of Information and Computational Science 2007年第2期4卷 821-828页

作者： Xu, Dong Li, Hua Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Graduate University Chinese Acad. of Sci. Beijing 100080 China

2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective moment invariants are generated theoretically by investigating the property of signed volume of a tetrahedron. The main part is the selection of permutation invariant cores for multiple integrals to generate independent and nonzero 3-D projective moment invariants. We give the conclusion that projective moment invariants don't exist strictly speaking because of their convergence problem.

关键词： computer vision

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Matching request profile and service profile for semantic web service discovery

Matching request profile and service profile for semantic we...

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2007 AAAI Workshop

作者： Peng, Hui Shi, Zhongzhi Qiu, Lirong Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China School of Computer Science and Engineering Hunan University of Science and Technology Xiang Tan 411201 China Graduate School Chinese Academy of Sciences 100039 Beijing China

ISBN: (纸本)9781577353386

OWL-S Service Profile provides a way to describe services offered by providers and services needed by requesters. But some items in the Profile are not very suitable for describing a requester's demands while some important information about the requester himself such as his identity which may play important role in precondition match are not considered in the Service Profile. In this paper we define an OWL compatible Request Profile ontology especially for service requesters to describe their special properties and their expectation about a service. Then a match algorithm is proposed to match service request described in Request Profile with service advertise described in Service Profile. The experiment results show that the match algorithm is efficient.

关键词： Web services

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

Reliable and Energy Efficient Protocol for Wireless Sensor N...

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第十二届全国容错计算学术会议

作者： KAN Baoqiang CAI Li XU Yongjun College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer Sy College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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IEEE International Test Conference

作者： Da Wang Xiaoxin Fan Xiang Fu Hui Liu Ke Wen Rui Li Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics (Shanghai) Company Limited Shanghai China

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ... 详细信息

关键词： Microprocessors Clocks Design for testability Circuit testing Logic testing Circuit faults Manufacturing Power dissipation CMOS technology Phase locked loops

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