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Frontiers of Massively Parallel Computation

作者： K.B. Theobald G.R. Gao T.L. Sterling Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering University of Delaware Newark DE USA NASA Jet Propulsion Laboratory /Center for Advanced Computing Research California Institute of Technology Pasadena CA USA

The Hybrid technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor processors, semiconductor memories with built-in processors, high-speed optical interconnects, and high-density holographic storage. While there are major challenges in all aspects of this project, those in processor architecture are the focus of this paper. Fundamental differences between RSFQ circuits and conventional semiconductor circuits, including a radical jump in clock speed, make today's processor design approaches inappropriate for HTMT. Sequential instruction dispatching, even within the lowest programming unit (a strand), will lead to unacceptably high latencies, hence poor performance. We propose alternative processor designs which use fine-grain synchronizations between individual instructions in order to avoid these bottlenecks.

关键词： Random access memory Optical buffering Holography Holographic optical components Delay computer architecture Optical interconnections Electrical capacitance tomography Quantum computing Clocks

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Identifying the capability of overlapping computation with communication

Identifying the capability of overlapping computation with c...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： A. Sohn J. Ku Y. Kodama M. Sato H. Sakane H. Yamana S. Sakai Y. Yamaguchi Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Real World Computing Tsukuba Research Center Tsukuba Ibaraki Japan

Overlapping computation with communication is central to obtaining high performance on distributed-memory multiprocessors. This report explicates the overlapping capability of two distributed-memory multiprocessors: the EM-X and IBM SP-2. The well-known bitonic sorting algorithm is selected for experiments. Various message sizes are used to determine when, where, how much and why overlapping takes place. Experimental results indicate that both multiprocessors would yield up to 30% to 40% overlap of communication time when the message size is approximately 1K integers. EM-X is found to be message-size insensitive yielding high overlap for various message sizes, while SP-2 was effective for the window of message size 512 to 2K integers.

关键词： Delay computer architecture Switches Distributed computing High performance computing Sorting Prototypes Laboratories Yarn Windows

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Parallel bidirectional heuristic search on the EM-4 multiprocessor

Parallel bidirectional heuristic search on the EM-4 multipro...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： A. Sohn M. Sato S. Sakai Y. Kodama Y. Yamaguchi Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Real World Computing Tsukuba Research Center Tsukuba Ibaraki Japan

Solving search problems takes a large amount of computational resources both in terms of execution time and memory usage. This report presents experimental results of Parallel Bidirectional Heuristic Search (PBiHS) on the 80-processor EM-4 multithreaded data-flow multiprocessor. The PBiHS searches from two directions in parallel while search in each direction is also performed in parallel. Important data structures are distributed to all processors to help reduce the execution time of realistic problem sizes down to a few seconds or less. We implement two search problems, the Eight Puzzle and the Tower of Hanoi, and execute on the target multiprocessor. Execution results demonstrate that the Parallel Bidirectional Heuristic Search can solve the tree depth 20-40 of the Eight-Puzzle and the 3-9 disks of the Tower of Hanoi in an optimal or near optimal number of iterations in less than two seconds, is highly scalable as it gives over 40-fold speedup on 80 processors, and yields on the average 10-fold improvement over unidirectional search for the 8-Puzzle while generating a far less number of nodes.< >

关键词： Search problems Poles and towers Artificial intelligence Concurrent computing Data structures Parallel processing Information science computer architecture Laboratories Buildings

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Cost-Efficient Deep Neural Network Placement in Edge Intelligence-Enabled Internet of Things

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ACM Transactions on Sensor Networks 1000年

作者： Hao Tian Xiaolong Xu Hongyue Wu Qingzhan Zhao Jianguo Dai Maqbool Khan State Key Laboratory for Novel Software Technology Nanjing University Nanjing Jiangsu China Nanjing China School of Software Nanjing University of Information Science and Technology Nanjing Jiangsu China Nanjing China College of Intelligence and Computing Tianjin University Tianjin China Tianjin China Geospatial Information Engineering Research Center College of Information Science and Technology Shihezi University Shihezi Xinjiang China Shihezi China Department of IT and Computer Science Pak-Austria Fachhochschule Institute of Applied Sciences and Technology Haripur Pakistan Haripur Pakistan

Edge intelligence (EI) integrates edge computing and artificial intelligence empowering service providers to deploy deep neural networks (DNNs) on edge servers in proximity to users to provision intelligent applications (e.g., autonomous driving) for ubiquitous Internet of Things (IoT) in smart cities, which facilitates the quality of experience (QoE) of users and improves the processing and energy efficiency. However, considering DNN is typically computational-intensive and resource-hungry, conventional placement approaches ignore the influence of multi-dimensional resource requirements (processor, memory, etc.), which may degrade the real-time performance. Moreover, with the increasing scale of geo-distributed edge servers, centralized decision-making is still challenging to find the optimal strategies effectively. To overcome these shortcomings, in this paper we propose a game theoretic DNN placement approach in EI-enabled IoT. First, a DNN placement optimization problem is formulated to maximize system benefits, which is proven to be \(\mathcal {N}\mathcal {P}\)-hard and model the original problem as an exact potential game (EPG). Moreover, an EPG-based DNN model placement algorithm, named EPOL, is designed for edge servers to make sub-optimal strategies independently and theoretical analysis is possessed to guarantee the performance of EPOL. Finally, real-world dataset based experimental results corroborate the superiority and effectiveness of EPOL.

关键词： Edge intelligence DNN placement Game theory Internet of Things

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GAHE: Geometry-Aware Embedding for Hyper-Relational Knowledge Graph Representation

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ACM Transactions on Multimedia computing, Communications, and Applications 1000年

作者： Zongsheng Cao Qianqian Xu Zhiyong Yang Yuan He Xiaochun Cao Qingming Huang State Key Laboratory of Information Security SKLOIS) Institute of Information Engineering Chinese Academy of Sciences China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences China Security Department of Alibaba Group China School of Cyber Science and Technology Shenzhen Campus Sun Yat-sen University China

Knowledge graphs have proven highly effective for learning representations of entities and relations, with hyper-relational knowledge graphs (HKGs) gaining increased attention due to their enhanced representation capabilities. Each fact in an HKG consists of a main triple supplemented by attribute-value qualifiers that provide additional contextual information. Due to the complexity of hyper-relations, HKGs typically contain complex geometric structures, such as hierarchical, ring, and chain structures, often mixed together. However, previous work mainly embeds HKGs into Euclidean space, limiting their ability to capture these complex geometric structures simultaneously. To address this challenge, we propose a novel model called Geometry Aware Hyper-relational Embedding (GAHE). Specifically, GAHE adopts a multi-curvature geometry-aware approach by modeling HKGs in Euclidean space (zero curvature), hyperbolic space (negative curvature), and hyperspherical space (positive curvature) in a unified framework. In this way, it can integrate space-invariant and space-specific features to accurately capture the diverse structures in HKGs. In addition, GAHE introduces a module termed hyper-relational subspace learning, which allocates multiple sub-relations for each hyper-relation. It enables the exploitation of abundant latent semantic interactions and facilitates the exploration of fine-grained semantics between attribute-value pairs and hyper-relations across multiple subspaces. Furthermore, we provide theoretical guarantees that GAHE is fully expressive and capable of modeling a wide range of semantic patterns for hyper-relations. Empirical evaluations demonstrate that GAHE achieves state-of-the-art results on both hyper-relational and binary-relational benchmarks.

关键词： Knowledge Graph Hyper-relational Learning Multicurvature Spaces Geometry Aware

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PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow architectures

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ACM Transactions on architecture and Code Optimization 1000年

作者： Shantian Qin Zhihua Fan Wenming li Zhen Wang Xuejun An Xiaochun Ye Dongrui Fan State Key Laboratory of Processors Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China State Key Laboratory of Processors Institute of Computing Technology Chinese Academy of Sciences Beijing China

Dataflow architectures are considered promising architecture, offering a commendable balance of performance, efficiency, and flexibility. Abundant prior works have been proposed to improve the performance of dataflow architectures. Nevertheless, these solutions can be further improved due to the lack of efficient data prefetching and flexible task scheduling. In this paper, we propose a novel dataflow architecture with adaptive prefetching and decentralized scheduling (PANDA). Firstly, we present an application-adaptive data prefetching method and on-chip memory microarchitecture designed to overlap memory access latency. Secondly, we introduce a decentralized dataflow scheduling approach and processing element (PE) microarchitecture aimed at improving hardware utilization. Experimental results show that in a wide range of real-world applications, PANDA attains up to 2.53 × performance improvement and 1.79 × energy efficiency improvement over the state-of-the-art dataflow architectures.

关键词： Prefetching Decentralized Dynamic Scheduling Reconfigurable On-chip Memory architecture

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Improving Deep Assertion Generation via Fine-Tuning Retrieval-Augmented Pre-trained Language Models

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ACM Transactions on Software Engineering and Methodology 1000年

作者： Quanjun Zhang Chunrong Fang Yi Zheng Yaxin Zhang Yuan Zhao Rubing Huang Jianyi Zhou Yun Yang Tao Zheng Zhenyu Chen Department of Computing Technologies Swinburne University of Technology Australia and State Key Laboratory for Novel Software Technology Nanjing University China State Key Laboratory for Novel Software Technology Nanjing University China School of Computer Science and Engineering Macau University of Science and Technology China Huawei Cloud Computing Technologies Co. Ltd. China Department of Computing Technologies Swinburne University of Technology Australia State Key Laboratory for Novel Software Technology Nanjing University China and Shenzhen Research Institute of Nanjing University China

Unit testing validates the correctness of the units of the software system under test and serves as the cornerstone in improving software quality and reliability. To reduce manual efforts in writing unit tests, some techniques have been proposed to generate test assertions automatically, including deep learning (DL)-based, retrieval-based, and integration-based ones. Among them, recent integration-based approaches inherit from both DL-based and retrieval-based approaches and are considered state-of-the-art. Despite being promising, such integration-based approaches suffer from inherent limitations, such as retrieving assertions with lexical matching while ignoring meaningful code semantics, and generating assertions with a limited training *** this paper, we propose a novel Retrieval-Augmented Deep Assertion Generation approach, namely RetriGen, based on a hybrid assertion retriever and a pre-trained language model (PLM)-based assertion generator. Given a focal-test, RetriGen first builds a hybrid assertion retriever to search for the most relevant test-assert pair from external codebases. The retrieval process takes both lexical similarity and semantical similarity into account via a token-based and an embedding-based retriever, respectively. RetriGen then treats assertion generation as a sequence-to-sequence task and designs a PLM-based assertion generator to predict a correct assertion with historical test-assert pairs and the retrieved external assertion. Although our concept is general and can be adapted to various off-the-shelf encoder-decoder PLMs, we implement RetriGen to facilitate assertion generation based on the recent CodeT5 model. We conduct extensive experiments to evaluate RetriGen against six state-of-the-art approaches across two large-scale datasets and two metrics. The experimental results demonstrate that RetriGen achieves 57.66% and 73.24% in terms of accuracy and CodeBLEU, outperforming all baselines with an average improvement of 50.66%

关键词： Unit Testing Assertion Generation Pre-trained Language Models AI4SE

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Multi-Agent Reinforcement Learning based Edge Content Caching for Connected Autonomous Vehicles in IoV

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ACM Transactions on Autonomous and Adaptive Systems 1000年

作者： Xiaolong Xu Linjie Gu Muhammad Bilal Maqbool Khan Yiping Wen Guoqiang Liu Yuan Yuan School of Software Jiangsu Province Engineering Research Center of Advanced Computing and Intelligent Services Nanjing University of Information Science and Technology China Changwang School of Honors Nanjing University of Information Science and Technology China Department of Computer and Electronics Systems Engineering Hankuk University of Foreign Studies Korea Department of IT and Computer Science Pak-Austria Fachhochschule-Institute of Applied Sciences and Technology Pakistan School of Computer Science and Engineering Hunan University of Science and Technology China School of Software Nanjing University of Information Science and Technology China School of Computer Science and Engineering Beihang University State Key Laboratory of Software Development Environment Zhongguancun Laboratory China

Connected Autonomous Vehicle (CAV) Driving, as a data-driven intelligent driving technology within the Internet of Vehicles (IoV), presents significant challenges to the efficiency and security of real-time data management. The combination of Web3.0 and edge content caching holds promise in providing low-latency data access for CAVs’ real-time applications. Web3.0 enables the reliable pre-migration of frequently requested content from content providers to edge nodes. However, identifying optimal edge node peers for joint content caching and replacement remains challenging due to the dynamic nature of traffic flow in IoV. Addressing these challenges, this article introduces GAMA-Cache, an innovative edge content caching methodology leveraging Graph Attention Networks (GAT) and Multi-Agent Reinforcement Learning (MARL). GAMA-Cache conceptualizes the cooperative edge content caching issue as a constrained Markov decision process. It employs a MARL technique predicated on cooperation effectiveness to discern optimal caching decisions, with GAT augmenting information extracted from adjacent nodes. A distinct collaborator selection mechanism is also developed to streamline communication between agents, filtering out those with minimal correlations in the vector input to the policy network. Experimental results demonstrate that, in terms of service latency and delivery failure, the GAMA-Cache outperforms other state-of-the-art MARL solutions for edge content caching in IoV.

关键词： Content Caching Reinforcement Learning Connected Autonomous Driving

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Advanced Parallel Processing Technologies 1

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丛书名： Lecture Notes in computer Science

1000年

作者： Chenggang Wu Albert Cohen

ISBN: (数字)9783642452932

ISBN: (纸本)9783642452925

This book constitutes the refereed post-proceedings of the 10th International Symposium on Advanced Parallel Processing Technologies, APPT 2013, held in Stockholm, Sweden, in August 2013. The 30 revised full papers presented were carefully reviewed and selected from 62 submissions. The papers cover a wide range of topics capturing some of the state of the art and practice in parallel architecture, parallel software, concurrent and distributed systems, and cloud computing, with a highlight on computing systems for big data applications.

关键词： Software Engineering Algorithm Analysis and Problem Complexity computer Communication Networks Operating Systems Programming Languages, Compilers, Interpreters

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Conceptual Modeling for Advanced Application Domains 1

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丛书名： Lecture Notes in computer Science

1000年

作者： Shan Wang Katsumi Tanaka Shuigeng Zhou Tok-Wang Ling Jihong Guan Dong-qing Yang Fabio Grandi Eleni E. Mangina Il-Yeol Song Heinrich C. Mayr

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