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检索条件"机构=Key Laboratory of Computer Architecture and System"
405 条 记 录,以下是121-130 订阅
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On diagnosis of multiple faults using compacted responses
On diagnosis of multiple faults using compacted responses
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作者: Ye, Jing Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-fo... 详细信息
来源: 评论
Improve accuracy of delay element by filtering false path for low power desychronized circuits
Improve accuracy of delay element by filtering false path fo...
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IEEE International Symposium on Circuits and systems (ISCAS)
作者: Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China
Desynchronized circuits outperform the synchronous counterparts in power, performance, robustness according to many studies, and delay elements are important components by mimicking the critical path delay of two arbi... 详细信息
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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T
A Case Study: Low Power Design-for-Testability Features of a...
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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)
作者: Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences
This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanomet... 详细信息
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A processor-DMA-based memory copy hardware accelerator
A processor-DMA-based memory copy hardware accelerator
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IEEE International Conference on Networking, architecture and Storage
作者: Su, Wen Wang, Ling Su, Menghao Liu, Su Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China
For many Operating systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accele... 详细信息
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Empirical design bugs prediction for verification
Empirical design bugs prediction for verification
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作者: Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China
Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is ... 详细信息
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Optimizing MPI alltoall communication of large messages in multicore clusters
Optimizing MPI alltoall communication of large messages in m...
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2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011
作者: Li, Qiang Huo, Zhigang Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Chinese Academy of Sciences Graduate University Beijing 100049 China
MPI Alltoall communication is widely used in many high performance computing (HPC) applications. In Alltoall communication, each process sends a distinct message to all other participating processes. In multicore clus... 详细信息
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Processes scheduling on heterogeneous multi-core architecture with hardware support
Processes scheduling on heterogeneous multi-core architectur...
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IEEE International Conference on Networking, architecture and Storage
作者: Hao, Shouqing Liu, Qi Zhang, Longbing Wang, Jian Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China
Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP sys... 详细信息
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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip  11
Vertical interconnects squeezing in symmetric 3D mesh Networ...
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Asia and South Pacific Design Automation Conference
作者: Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combinin... 详细信息
来源: 评论
A resilient on-chip router design through data path salvaging  11
A resilient on-chip router design through data path salvagin...
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Asia and South Pacific Design Automation Conference
作者: Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permane... 详细信息
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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation  11
Wear rate leveling: Lifetime enhancement of PRAM with endura...
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Design Automation Conference
作者: Jianbo Dong Lei Zhang Yinhe Han Ying Wang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traff... 详细信息
来源: 评论