检索结果-内蒙古大学图书馆

High efficient memory race recording scheme for parallel program deterministic replay under multi-core architecture

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2012年第1期49卷 64-75页

作者： Liu, Lei Huang, He Tang, Zhimin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China MIPS Technologies Shanghai 210021 China

Current shared memory multi-core and multiprocessor systems are nondeterministic. When these systems execute a multithreaded application, even if supplied with the same input, they could produce a different output each time. It frustrates debugging and limits the ability to properly test multithreaded code, and is becoming a major stumbling block to the much-needed widespread adoption of parallel programming. The support for deterministic replay of multithreaded execution is greatly helpful in finding concurrency bugs. A memory race recording scheme, named Rainbow, is proposed. Its core idea is to make inter-thread communications fully deterministic. The unique feature of Rainbow is that it precisely sets up happens-before relationships between conflicting memory operations among different threads. By using effective, bloom-filter based, coherence history queue, Rainbow removes redundant happens-before relations implied in the already generated log and enables a compact log. Rainbow adds the modest hardware to the base multi-core processors, and the coherence protocol is unmodified. The analysis results show that Rainbow reduces the log size by 17% of a state-of-the-art scheme, and the records execution speed is similar to that of release consistency (RC) execution and replays at about 93% of its speed. The determinism can be provided with little performance cost using our architecture proposals on the state-of-the-art hardware, and the software-only approaches can be utilized on existing systems without problem.

关键词： Parallel programming

来源：评论

学校读者我要写书评

暂无评论

Optimizing MPI Alltoall communications in multicore clusters

引用

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2013年第8期50卷 1744-1754页

作者： Li, Qiang Sun, Ninghui Huo, Zhigang Ma, Jie High Performance Computer Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100039 China

MPI Alltoall is an important collective operation. In multicore clusters, many processes run in a node. On the one hand, shared memory can be adopted to optimize Alltoall communications of small messages by leader-based schemes. However, as these schemes adopt a fixed number of leader processes, the optimal performance can't be obtained for all small messages. On the other hand, processes within a node contend for the same network resource. In Alltoall communications of large messages, many synchronization messages are used. Nevertheless, the contention makes their latency increase many times and the synchronization overhead can't be ingored. To solve these problems, two optimizations are presented. For small messages, the PLP method adopts changeable numbers of leader processes. For large messages, the LSS method reduces the number of synchronization messages from 3N to 2√N. The evaluations prove two methods. For small messages, the PLP method always obtains optimal performance. For large messages, the LSS method brings almost constant improvement percentage. The performance is improved by 25% for 32 KB and 64 KB messages.

关键词： Synchronization

来源：评论

学校读者我要写书评

暂无评论

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

nGFSIM : A GPU-based fault simulator for 1-to-n detection an...

引用

IEEE International Test Conference

作者： Huawei Li Dawen Xu Yinhe Han Kwang-Ting Cheng Xiaowei Li Department of Electrical and Computer Engineering University of California Santa Barbara USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the fault coverage of one-to n-detection for any specified integer n using only a single run of fault simulation. nGFSIM, which explores the massive parallelism in the GPU architecture and optimizes the memory access and usage, enables accelerated fault simulation without the need of fault dropping. We show that nGFSIM offers a 25X speedup in comparison with a commercial tool and enables new applications in test selection.

关键词： Circuit faults Graphics processing unit Integrated circuit modeling Instruction sets Logic gates Computational modeling Kernel

来源：评论

学校读者我要写书评

暂无评论

Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

来源：评论

学校读者我要写书评

暂无评论

A Scalable Scan architecture for Godson-3 Multicore Microprocessor

A Scalable Scan Architecture for Godson-3 Multicore Micropro...

引用

Asian Test Symposium (ATS)

作者： Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (test access mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a data-synchronous-comparator (DSC) is proposed for comparing the scan responses of the identical cores.

关键词： Multicore processing Microprocessors Switches computer architecture system testing Laboratories Large-scale systems Linear predictive coding Delay Logic testing

来源：评论

学校读者我要写书评

暂无评论

A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEWORK FOR MOBILE TERMINALS

A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEW...

引用

2012 IEEE 2nd International Conference on Cloud Computing and Intelligence systems

作者： Pingyi Wang Jingling Zhao Qing Liao School of Computer Science Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications

The increasing number of mobile terminals facilitates the development of context-aware applications. However, developing a context aware application is still a complex work, which involves mechanisms of context acquisition and context processing. In order to release the developer’s burden, many context aware frameworks emerged. But none of them yet has sufficient consideration of mobile environment characteristics. Besides, restricted to the mobile platform, the developed application could not achieve cross-platform deployment. A cross-platform context-aware application developing framework for mobile terminals is proposed in this paper. This framework could shield system differences, centralize context acquisition, context modeling, context storing, context interpretation and context aggregation for many context aware applications on the same terminal. Applying the framework, data of same sensor would not be duplicated processed by many context aware applications. Context aware application would be built faster. And mobile terminal resources would be used more efficiently.

关键词： Context-awareness Cross-platform Mobile terminal Framework

来源：评论

学校读者我要写书评

暂无评论

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

Flip-Flop Selection for Transition Test Pattern Reduction Us...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine the respective advantages of the two approaches, by replacing a small number of selected regular scan cells with enhanced scan cells, thus to reduce the overall volume of transition delay test patterns effectively. Moreover, higher fault coverage can also be obtained by this approach compared to the standard LOC approach. Experimental results on larger ISCAS-89 and ITC-99 benchmark circuits using a commercial test generation tool show that the volume of test patterns can be reduced by over 70% and the transition delay fault coverage can be improved by up to 8.7%.

关键词： Flip-flops Delay Circuit testing Lab-on-a-chip Circuit faults Test pattern generators system testing Hardware Costs Timing

来源：评论

学校读者我要写书评

暂无评论

An abstraction-guided simulation approach using Markov models for microprocessor verification 10

An abstraction-guided simulation approach using Markov model...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Tao Zhang Tao Lv Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.

关键词： Microprocessors Testing Computational modeling Engines Data mining computer simulation Power system modeling Laboratories computer architecture Instruction sets

来源：评论

学校读者我要写书评

暂无评论

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance system recovery computer networks Region 4 Shape Laboratories computer architecture

来源：评论

学校读者我要写书评

暂无评论

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

引用

International Conference on Parallel and Distributed systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：