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4th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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Profile guided optimization for dataflow predication

Profile guided optimization for dataflow predication

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Li, Wang Hong, An Yongqing, Ren Yaobin, Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424426836

Dataflow predication provides a lightweight full support for predicated execution in dataflow-like architectures. One of its major overhead is the large amounts of fanout trees for distributing predicates to all dependant instructions. Conventional optimizations are predicating only the heads or tails of dataflow chains. Predicating tails offers more speculation but leads to resource contentions and power consumption increasing. Predicating heads is power efficient but reduces speculation and instruction level parallelism. This paper introduces a profile guided technique to combine these optimizations. It uses profiling feedback to guide the compiler in deciding to predicate at the head or tail. By predicating tails on hot paths and predicating heads on infrequent paths, this technique can get performance, power and resource efficiency Performance evaluation result shows that profile guided optimization performs better in removing fanout trees. It has 10.6% speedup over always predicating heads and 2.5% speedup over always predicating tails in performance. © 2008 IEEE.

关键词： Forestry

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CuHMMer: A load-balanced CPU-GPU cooperative bioinformatics application

CuHMMer: A load-balanced CPU-GPU cooperative bioinformatics ...

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2010 International Conference on High Performance Computing and Simulation, HPCS 2010

作者： Yao, Ping An, Hong Xu, Mu Liu, Gu Li, Xiaoqiang Wang, Yaobin Han, Wenting School of Computer Science and Technology University of Science and Technology of China Hefei 230027 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424468287

GPUs have recently been used to accelerate data-parallel applications for they provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power. Most of those applications use CPU as a controller who decides when GPUs run the computing-intensive tasks. This CPU-control-GPU-compute pattern wastes much of CPU's computational power. In this paper, we present a new CPU-GPU cooperative pattern for bioinformatics applications which can use both of CPU and GPU to compute. This pattern includes two parts: 1) the load-balanced data structure which manages data to keep the computational efficiency of GPU high enough when the length distribution of sequences in a sequence database is very uneven;2) multi-threaded code partition which schedules computing on CPU and GPU in a cooperative way. Using this pattern, we develop CuHMMer based on HMMER which is one of the most important algorithms in bioinformatics. The experimental result demonstrates that CuHMMer get 13x to 45x speed up over available CPU implementations and could also outperform the traditional CUDA implementations which use CPU-control-GPU-compute pattern. ©2010 IEEE.

关键词： Graphics processing unit

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A Wire delay scalable stream processor architecture

A Wire delay scalable stream processor architecture

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Guang, Xu Hong, An Ming, Cong Fang, Wang Yongqing, Ren Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Science Beijing 100080 China

ISBN: (纸本)9781424426836

Growing on-chip wire delays will cause many future microarchitecture to be distributed. The centralized control and data transmission of the conventional stream processor need to be improved, the hardware resources within a single stream processor become tiles on one or more switched micronetworks. In this paper, we introduce the architecture of the tiled stream processor which aims to adapt to the increasing wire resistance. The tiled stream processor consists of tile arrays, the distributed control and data network which connect tiles. The tile arrays include the five type of reused tiles, the control packet transferred in the control network traverse the tile in a cycle. The architecture of the tiled stream processor supports explicit data management in the hardware way and include two level register hierarchy which are controlled by the software to capture the data locality. The tiled stream processor use the stream programming model which are StreamC/KernelC language, the kernel microcode executed in the tiled arrays are statically scheduled into instruction blocks and execute dynamically in an dataflow order. Finally, we discuss features that affect the kernel performance, with the one cycle routing delay the simulator can achieve an average of 10IPC in eight kernels. © 2008 IEEE.

关键词： computer architecture

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Statistical static timing analysis for circuit aging prediction

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The Journal of China Universities of Posts and Telecommunications 2021年第2期28卷 14-23页

作者： Duan Shengyu Zhai Dongyao Lu Yue Shanghai Engineering Research Center of Intelligent Computing System Shanghai UniversityShanghai 200444China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Electronics and Computer Science University of SouthamptonSouthamptonUK

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit *** results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic *** amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design *** this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI *** consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability *** method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

关键词： bias temperature instability(BTI) reliability prediction statistical static timing analysis(SSTA)

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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Regular Paper: A Study of Architectural Optimization Methods in Bioinformatics Applications

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The International Journal of High Performance Computing Applications 2007年第3期21卷 371 - 384页

作者： G. Tan L. Xu Z. Dai S. Feng N. Sun KEY LABORATORY OF COMPUTER SYSTEM AND ARCHITECTURE INSTITUTE OF COMPUTING TECHNOLOGY CHINESE ACADEMY OF SCIENCES BEIJING CHINA KEY LABORATORY OF COMPUTER SYSTEM AND ARCHITECTURE INSTITUTE OF COMPUTING TECHNOLOGY CHINESE ACADEMY OF SCIENCES BEIJING CHINA

Studies in the optimization of sequence alignment have been carried out in bioinformatics. In this paper, we have focused on two aspects: memory usage and execution time. Our study suggests that cache memory does not have a significant effect on system performance. Our attention then turns to optimize Smith—Waterman's algorithm. Two instruction level methods have been proposed and 2—8 fold speed improvements have been observed after the optimization has been implemented. Further improvements on system performance have been achieved by overlapping computation with system I/O usage.

关键词： bioinformatics sequence alignment cache memory instruction level parallelism I/O overlapping

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A low overhead on-chip path delay measurement circuit

A low overhead on-chip path delay measurement circuit

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18th Asian Test Symposium, ATS 2009

作者： Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China

ISBN: (纸本)9780769538648

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy. © 2009 IEEE.

关键词： Timing circuits

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A low-complexity synchronization based cache coherence solution for many cores

A low-complexity synchronization based cache coherence solut...

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IEEE 9th International Conference on computer and Information Technology, CIT 2009

作者： Lin, Wei Fan, DongRui Huang, He Yuan, Nan Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the "flag". We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included. © 2009 IEEE.

关键词： Synchronization

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Address remapping for static NUCA in noc-based degradable chip-multiprocessors

Address remapping for static NUCA in noc-based degradable ch...

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16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010

作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542898

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme. © 2010 IEEE.

关键词： Network-on-chip

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