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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

引用

2007 IEEE International Test Conference, ITC

作者： Wang, Da Fan, Xiaoxin Fu, Xiang Liu, Hui Wen, Ke Li, Rui Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Beijing China Co. Ltd. Shanghai China

ISBN: (纸本)1424411289

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals. © 2007 IEEE.

关键词： Design for testability

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Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Test Generation for Crosstalk Glitches Considering Multiple ...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Minjin Zhang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise considering multiple coupling effects and propose a novel test generation technique for this problem. A multiple crosstalk-induced glitch fault (MCGF) model is introduced, which gives information on one or more sub-paths to be sensitized to generate transitions coupled to a victim line. The test for an MCGF is a 2-vector pattern that sensitizes the transition signal along the sub-path to each aggressor line at the maximum aggressive time (MAT), and propagates the signal on a victim line to an output. A new structure, transition map (TM), is proposed to record all the possible arrival time of a line. The MAT of a victim line is calculated based on effective coupling capacitance (ECC). Therefore, the crosstalk-induced effects can be effectively identified, and exactly activated using the generated test patterns. Experiments on ISCAS89 benchmark circuit show that the proposed technique can be applied to circuits of reasonable sizes within acceptable time.

关键词： Crosstalk Circuit faults Timing Test pattern generators system testing Noise generators Coupling circuits Capacitance Circuit noise Automatic test pattern generation

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Deterministic Circular Self Test Path

Deterministic Circular Self Test Path

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第十二届全国容错计算学术会议

作者： WEN Ke HU Yu LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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Protein Structure Prediction Based on a Domain Clustering Database

Protein Structure Prediction Based on a Domain Clustering Da...

引用

The 1st International Conference on Bioinformatics and Biomedical Engineering(iCBBE 2007)(首届IEEE生物信息与生物医学工程国际会议)

作者： Zhaoyun Ma Lin Xu Zhiyong Liu Fa Zhang Shengzhong Feng Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Comput Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Comput

Homology modeling, as a successful protein structure prediction method, has two major deficiencies, I.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well Compared with other alignment methods, such as T-coffee and Smith-Waterman, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore,the quality of protein structure prediction can be improved.

关键词： structure prediction profile domain

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Fault Tolerance Mechanism in Chip Many-Core Processors

Fault Tolerance Mechanism in Chip Many-Core Processors

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第十二届全国容错计算学术会议

作者： ZHANG Lei HAN Yinhe LI Huawei LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8％ degradation with negligible computing time.

关键词： chip many-core processors yield fault tolerance reconfiguration network-on-chip

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On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

On Selection of Testable Paths with Specified Lengths for Fa...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Xiang Fu Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

关键词： faster-than at-speed testing testable path selection small delay defect

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Online Distributed Fault Detection of Sensor Measurements

Online Distributed Fault Detection of Sensor Measurements

引用

第十二届全国容错计算学术会议

作者： GAO Jianliang XU Yongjun LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30％ of the sensors are faulty, over 95％ of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.

关键词： wireless sensor networks fault diagnosis fault detection fault tolerance spatial correlation

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An Efficient Algorithm for Finding a Universal Set of Testable Long Paths

An Efficient Algorithm for Finding a Universal Set of Testab...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Zijian He Tao Lv Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ

In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.

关键词： delay testing testable long paths

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On-the-fly Reduction of Stimuli for Functional Verification

On-the-fly Reduction of Stimuli for Functional Verification

引用

2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Qi Guo Weiwu Hu Tianshi Chen Haihua Shen Yunji Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.

关键词： Functional Verification Stimuli Reduction Redundancy Online Learning Godson-2

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Software-Based Self-Testing of Processors Using Expanded Instructions

Software-Based Self-Testing of Processors Using Expanded Ins...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Ying Zhang Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8％ stuck-at fault coverage, which is close to that of the full-scan test generation method. In addition, it can cut down 57％ test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.

关键词： Software-Based Self-Test Automatic Test Instruction Generation Instruction-Level Constraint On-Line Test

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