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检索条件"机构=Key Laboratory of Computer System and Architecture"

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Test cost efficiency exploration for CMT processors

Test cost efficiency exploration for CMT processors

引用

IEEE Region 10 International Conference TENCON

作者： Jia Li Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Chip multi-threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve very short test time and low test data volume under stringent power constraints with low area overhead.

关键词： Costs Bandwidth system testing computer architecture Frequency Hardware Thermal management Power dissipation Network-on-a-chip Laboratories

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Energy-Efficient Input Buffer Design using Data-Transition Oriented Model

Energy-Efficient Input Buffer Design using Data-Transition O...

引用

International Symposium on Integrated Circuits (ISIC)

作者： Jun Wang Kun Huang Ge Zhang Weiwu Hu Feng Zhang Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Network-on-chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in chip multi-processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here. And using our method, a suit of benchmarks, SPLASH-2, are executed to evaluate the designs with different physical parameters and circuit structures. The simulations are based on 90 nm CMOS process, and the input buffer with 64-bit width and 16-entry depth is recommended for more energy-efficiency.

关键词： Energy efficiency Network-on-a-chip Energy consumption Circuit simulation Integrated circuit interconnections Bandwidth Laboratories computer networks computer architecture Content addressable storage

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Impact-factor-guided X-filling for peak power reduction during test

Impact-factor-guided X-filling for peak power reduction duri...

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IEEE Region 10 International Conference TENCON

作者： Jia Li Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Peak power during testing system-on-chip (SoC) circuits is a challenging issue for both reliability and yield. Because test vectors always try to activate as many faults as possible in the capture cycles, peak power during test usually happens in these cycles. X-filling is one effective way to reduce transitions happened in capture cycles to reduce peak power during test. However, its efficiency is limited and needs well exploration. This paper proposes an X impact-factor-metric to estimate the impact of filling one X bit on other X bits in test cube. This metric is utilized to efficiently guide the X-filling to reduce the capture power. We call it impact-factor-Guided (IFG) X-filling. Experimental results on larger ISCAS'89 benchmark circuits show that the average and maximum capture power can be reduced through our IFG X-filling by 65% and 31% on average, respectively.

关键词： Circuit testing Power dissipation Sequential analysis system testing CMOS technology system-on-a-chip Power system reliability Filling Reliability engineering Power engineering and energy

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Eliminating data invalidation in debugging multiple-clock chips

Eliminating data invalidation in debugging multiple-clock ch...

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China

ISBN: (纸本)9783981080179

A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data invalidation might occur when it comes to multiple-clock chips. In this paper, we analyze the possible data invalidation, including data repetition and data loss, when stopping and resuming a multiple-clock chip. Furthermore, we propose an efficient solution to eliminate data repetition and data loss. Theoretical analysis and simulation experiments are both conducted for the proposed solution. We implement the proposed Design-for-Debug (DfD) circuit with SMIC 0.18/Ltm technology and simulate the data transfer across clock domains using SPICE tool. The results show that both data repetition and data loss can be avoided with the proposed solution, even if metastability occurs. © 2011 EDAA.

关键词： Clocks

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T2- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip

T2- TAM:Reusing infrastructure resource to provide parallel ...

引用

International Conference on ASIC

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing

Reusing network-on-chip (NoC) as test-access-mechanism (TAM) has been adopted to transfer test data to embedded cores. However, an observation shows that compared to NoC-reuse TAM, some bus-based TAM are able to achieve better results in test time due to its fine-grained scheduling unit. This paper proposed a new TAM named Test Tree(T 2 ). T 2 TAM could be built by reusing the hardware resources of routers instead of reusing the packet-based NoC. Though implementing DFT design on routers, the T2TAM can achieve wire utilization and adopts fine-grained basic scheduling. Besides, to address the problem of testing large number of homogeneous cores, T 2 -TAM is proposed to facilitate multicasting stimuli to homogeneous cores to save test time. Experimental results show that the test cycles could be reduced up to 38% in comparison with the work reusing NoC as TAM with only 0.3% DFT overhead.

关键词： Testing Network-on-a-chip Wires Rails Scheduling algorithm Hardware Design for testability Tail Payloads Protocols

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An ultra-fast hybrid simulation framework for ASIP

An ultra-fast hybrid simulation framework for ASIP

引用

2011 18th IEEE International Conference on Electronics, Circuits and systems, ICECS 2011

作者： Qiu, Ji Gao, Xiang Jiang, Yifei Xiao, Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Science Beijing 100190 China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL United States

ISBN: (纸本)9781457718458

ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge. © 2011 IEEE.

关键词： Software design

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Optimizing web browser on many-core architectures

Optimizing web browser on many-core architectures

引用

2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Fan, Lingjun Shi, Weisong Tang, Shibin Yan, Chenggang Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Academy of Sciences Graduate University Beijing China Department of Computer Science Wayne State University Detroit United States

ISBN: (纸本)9780769545646

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with onchip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount. © 2011 IEEE.

关键词： Data transfer

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

引用

18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

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Research on I/Q unbalanced channel reciprocity calibration algorithm in massive MIMO system 3

Research on I/Q unbalanced channel reciprocity calibration a...

引用

3rd International Conference on Mechanical, Electronic and Information Technology Engineering, ICMITE 2017

作者： Cui, Jinming Yin, Liang Ma, Yue Li, Shufang Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China School of Computer Science Beijing University of Posts and Telecommunications Beijing100876 China

Massive MIMO system uses the transmitter channel state information (CSI) to preprocess the transmitted data, which can effectively reduce the interference and enhance the Massive MIMO system capacity. In the actual transmission process, reciprocity is subject to many factors, resulting in application difficulties. In this paper, we mainly study the influence of RF device's noncardiosis on channel reciprocity of Massive MIMO system. Combined with channel estimation based on pilot signal and FRRH subspace tracking algorithm, this paper proposes a channel reciprocity calibration method for Massive MIMO. Finally, the compensation effect of the compensation algorithm is verified by simulation. © The Authors, published by EDP Sciences, 2017.

关键词： MIMO systems

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Spatial throughput characterization in cognitive radio networks with threshold-based opportunistic spectrum access

Spatial throughput characterization in cognitive radio netwo...

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作者： Song, Xiaoshi Yin, Changchuan Liu, Danpu Zhang, Rui Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China Department of Electrical and Computer Engineering National University of Singapore Singapore117576 Singapore

This paper studies the opportunistic spectrum access (OSA) of the secondary users in a large-scale overlay cognitive radio (CR) network. Two threshold-based OSA schemes, namely the primary receiver assisted (PRA) protocol and the primary transmitter assisted (PTA) protocol, are investigated. Under the PRA/PTA protocols, a secondary transmitter (ST) is allowed to access the spectrum only when the maximum signal power of the received beacons/pilots sent from the active primary receivers/transmitters (PRs/PTs) is lower than a certain threshold. To measure the resulting transmission opportunity for the secondary users by the proposed OSA protocols, the concept of spatial opportunity, which is defined as the probability that an arbitrary location in the primary network is detected as a spatial spectrum hole, is introduced and then evaluated by applying tools from stochastic geometry. Based on spatial opportunity, the coverage (non-outage transmission) performance in the overlay CR network is analyzed. With the obtained results of spatial opportunity and coverage probability, we finally characterize the spatial throughput, which is defined as the average spatial density of successful transmissions in the primary/secondary network, under the PRA and PTA protocols, respectively. © 1983-2012 IEEE.

关键词： Cognitive radio

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