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检索条件"机构=Key Laboratory of Computer System and Architecture"

共 402 条记录，以下是141-150 订阅

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A testability-aware low power architecture

A testability-aware low power architecture

引用

25th IEEE International system-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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A processor-DMA-based memory copy hardware accelerator

A processor-DMA-based memory copy hardware accelerator

引用

IEEE International Conference on Networking, architecture and Storage

作者： Su, Wen Wang, Ling Su, Menghao Liu, Su Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

For many Operating systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage of a proposed Direct Memory Access (DMA) engine in the processor which overcomes many conventional DMA engine shortcomings. Experimental results show that the proposed hardware solution achieves a speedup of 14.79 compared with the optimized software solution and an overlap of 81.8% in computing and data transfer on average. © 2011 IEEE.

关键词： Engines

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Cache locking for network processing acceleration

Cache locking for network processing acceleration

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2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： Su, Wen Gao, Xiang Wang, Jing You, Ruibang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769547015

With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency. © 2012 IEEE.

关键词： Locks (fasteners)

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Simplified Multi-Ported Cache in High Performance Processor

Simplified Multi-Ported Cache in High Performance Processor

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Hao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

The memory bandwidth demands of modern microprocessors require the use of a multi-ported cache to achieve peak performance. However, multi- ported caches are costly to implement. In this paper we propose technique for using a simplified dual-ported cache instead, which is mostly composed of single- ported SRAMs, without decreasing the performance of the processor apparently. We evaluate this technique using realistic applications that include the operating system. Our technique using a simplified multi-ported banking cache, reduces the delay of select logic in LSQ by 16.1%, and achieves 98.1% of the performance of an ideal dual-ported cache.

关键词： Microprocessors Costs Delay Bandwidth Banking Clocks Laboratories High performance computing computer architecture Operating systems

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Efficient Optimization Methodology in Early-Stage Design of Mesh-structured On-Chip Power/Ground(P/G) Networks

Efficient Optimization Methodology in Early-Stage Design of ...

引用

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Zu-ying Luo Department of Electronics Beijing Normal University Key Laboratory of Computer System and Architecture ICTCAS

ISBN: (纸本)1424401607

Due to decreasing supply voltages and increasing power consumption of today’s VLSI chips,IR drops on on-chip power/ground(P/G) grids have to be explicitly considered during floor-planning stage in the today’s physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floor-planning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end *** this paper, we present a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing ***[11],we have proposed the approximate current distribution(ACD) simulation method and the OSMACD optimization approach for early-stage single-level P/G meshes].In this work,a feasible theory is induced to directly compute the optimal solutions OSMACD for practical double-mesh P/G grids of high-end *** results show that OS DMACD matches very well with the exact counterparts inefficiently obtained with ICCG,which can leads to significant speedup in the today IR-drop aware floor-planning.

关键词： picogram Floor plans Power consumption grids Grates system-on-chip computer chips iridium

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Optimizing Parallel Kinetic Monte Carlo Simulation by Communication Aggregation and Scheduling

Optimizing Parallel Kinetic Monte Carlo Simulation by Commun...

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2015大数据技术及应用论坛

作者： Baodong Wu Shigang Li Yunquan Zhang State Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Kinetic Monte Carlo(KMC) algorithm has been widely applied for simulation of radiation damage, grain growth and chemical reactions. To simulate at a large temporal and spatial scale, domain decomposition is commonly used to parallelize the KMC algorithm. However, through experimental analysis, we find that the communication overhead is the main bottleneck which affects the overall performance and limits the scalability of parallel KMC algorithm on large-scale clusters. To alleviate the above problems, we present a communication aggrega‐tion approach to reduce the total number of messages and eliminate the commu‐nication redundancy, and further utilize neighborhood collective operations to optimize the communication scheduling. Experimental results show that the opti‐mized KMC algorithm exhibits better performance and scalability compared with the well-known open-source library—SPPARKS. On 32-node Xeon E5-2680 cluster(total 640 cores), the optimized algorithm reduces the total execution time by 16 %, reduces the communication time by 50 % on average, and achieves 24 times speedup over the single node(20 cores) execution.

关键词： Domain decomposition Communication aggregation Communication scheduling Neighborhood collectives

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Design and Implementation of Floating Point Stack on General RISC architecture

Design and Implementation of Floating Point Stack on General...

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Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Xuehai Qian He Huang Hao Zhang Guoping Long Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents a framework for implementing the X86 FP stack used in an x86-compliant processor based on a general RISC architecture. Architectural supports are added to a typical RISC architecture to maintain the FP stack status. Some speculative techniques are applied to the decode stage to enable pipelined and efficient FP operations. An optimized register renaming scheme is proposed to eliminate redundant micro-ops in FP programs, resulting in an increased performance while mitigating the burden on register rename table. The simulation results show that on average more than 10% fmov micro-ops are removed. Elimination of micro-ops significantly speeds up the execution of programs. The IPC increases are as high as 30% for some programs, and near 10% on average

关键词： Reduced instruction set computing Registers computer architecture Decoding Helium Laboratories Design methodology Prototypes Analytical models Performance analysis

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DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance

DMA cache: Using on-chip storage to architecturally separate...

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IEEE Symposium on High-Performance computer architecture

作者： Dan Tang Yungang Bao Weiwu Hu Mingyu Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424456581

As technology advances both in increasing bandwidth and in reducing latency for I/O buses and devices, moving I/O data in/out memory has become critical. In this paper, we have observed the different characteristics of I/O and CPU memory reference behavior, and found the potential benefits of separating I/O data from CPU data. We propose a DMA cache technique to store I/O data in dedicated on-chip storage and present two DMA cache designs. The first design, Decoupled DMA Cache (DDC), adopts additional on-chip storage as the DMA cache to buffer I/O data. The second design, Partition-Based DMA Cache (PBDC), does not require additional on-chip storage, but can dynamically use some ways of the processor's last level cache (LLC) as the DMA cache. We have implemented and evaluated the two DMA cache designs by using an FPGA-based emulation platform and the memory reference traces of real-world applications. Experimental results show that, compared with the existing snooping-cache scheme, DDC can reduce memory access latency (in bus cycles) by 34.8% on average (up to 58.4%), while PBDC can achieve about 80% of DDC's performance improvements despite no additional on-chip storage.

关键词： Cache storage Delay Bandwidth Buffer storage system-on-a-chip Laboratories computer architecture Emulation Throughput Hard disks

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

引用

作者： Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China

ISBN: (纸本)9783981080179

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented. © 2011 EDAA.

关键词： Neural networks

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IFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing 08

IFill: An Impact-Oriented X-Filling Method for Shift- and Ca...

引用

2008 Design, Automation and Test in Europe (DATE 2008), vol.3

作者： Jia LI Qiang XU Yu HU Xiaowei LI Key Laboratory of Computer System and Architecture ICT CAS Beijing China and Graduate University of Chinese Academy of Sciences Beijing China The Chinese University of Hong Kong Key Laboratory of Computer System and Architecture ICT CAS Beijing China

ISBN: (纸本)9783981080131

In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed technique.

关键词： scan-based testing power reduction Electric circuits Power (Psychology) Energy sources circuit switching scanning reduction

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