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Optimizing MPI alltoall communication of large messages in multicore clusters

Optimizing MPI alltoall communication of large messages in m...

引用

2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Li, Qiang Huo, Zhigang Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Chinese Academy of Sciences Graduate University Beijing 100049 China

ISBN: (纸本)9780769545646

MPI Alltoall communication is widely used in many high performance computing (HPC) applications. In Alltoall communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in Alltoall communication. However, many small synchronization messages are required in Alltoall communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of Alltoall communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2√N. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of Alltoall communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%. © 2011 IEEE.

关键词： Synchronization

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Testing content addressable memories using instructions and march-like algorithms

Testing content addressable memories using instructions and ...

引用

15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma Yunji, Chen Menghao, Su Zichu, Qi Heng, Zhang Weiwu, Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100080 China Graduate University Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results. © 2008 IEEE.

关键词： system-on-chip

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DCMTs: Supporting dynamically created migratory threads

DCMTs: Supporting dynamically created migratory threads

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International Conference on Computational Science and Engineering

作者： Zhu, Yueting Zhang, Wu Jiang, Hai Lei, Yu Peng, Junjie Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science Arkansas State University Jonesboro AR United States Department of Computer Science and Engineering University of Texas Arlington TX United States Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780769543239

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach. © 2010 IEEE.

关键词： Fault tolerance

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A differential public PUF design for lightweight authentication 16

A differential public PUF design for lightweight authenticat...

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2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021

作者： Duan, Shengyu Sai, Gaole School of Computer Engineering and Science Shanghai University Shanghai200444 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (纸本)9783800755899

Physical Unclonable Functions (PUFs) have emerged as a promising primitive to provide a hardware keyless security mechanism for integrated circuit applications. Public PUFs (PPUFs) address the crucial PUF vulnerability of requiring databases to store the secrete reference information. This paper investigates one of the PPUF families, differential PPUF (dPPUF), which exploits complexly interacted logic to create time gap between actual execution and simulation, and to prevent simulation attacks. Conventional dPPUFs have high costs. We observe the repressers have large impact on simulation time, but take a great proportion in current dPPUF structure. We thereby present a represser network with specially designed interconnection and shared logic, to maintain a high circuit complexity and to reduce the area cost. We show the proposed dPPUF has similar resilience over simulation attacks as the conventional design. Area cost can be reduced by up to 44%, and thus the proposed design can be used for lightweight authentication. © VDE VERLAG GMBH.

关键词： Authentication

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MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

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IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： system recovery system-on-a-chip Program processors Bandwidth Load management Throughput Scalability

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Low Power Techniques on a High Speed Floating-point Adder Design

Low Power Techniques on a High Speed Floating-point Adder De...

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IEEE International Conference on Integration Technology (ICIT)

作者： Ge Zhang Kun Huang Haihua Shen Feng Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

A 64 bit low power, high speed floating-point adder design is presented in this paper. The proposed floating-point adder is based on dual path architecture, and both dynamic and leakage power are reduced by exploiting architecture opportunities to minimize switching activity and maximize the stack effect of the circuits concurrently. Experimental result based on 130 nm CMOS standard cell design shows that average power consumptions of the FP adder can be reduced by 61.4% with proposed low power techniques.

关键词： Adders Energy consumption Microprocessors Delay computer architecture Laboratories Switching circuits Central Processing Unit CMOS logic circuits Logic design

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GenerOS: An asymmetric operating system kernel for multi-core systems

GenerOS: An asymmetric operating system kernel for multi-cor...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Qingbo Yuan Jianbo Zhao Mingyu Chen Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Compute Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424464425

Due to complex abstractions implemented over shared data structures protected by locks, conventional symmetric multithreaded operating system kernel such as Linux is hard to achieve high scalability on the emerging multi-core architectures, which integrate more and more cores on a single die. This paper presents GenerOS - a general asymmetric operating system kernel for multi-core systems. In principal, GenerOS partitions processing cores into application core, kernel core and interrupt core, each of which is dedicated to a specified function. In implementation, we conduct a delicate modification to Linux kernel and provide the same interface as Linux kernel so that GenerOS is compatible with legacy applications. The better performance of GenerOS mainly benefits from: (1) Applications run on their own cores with minimal interrupt and kernel support; (2) Every kernel service is encapsulated in to a serial process so that there will be fewer contentions than conventional symmetric kernel; (3) A slim schedule policy is used in the kernel core to support schedule between system calls with low overhead. Experiments with two typical workloads on 16-core AMD machine show that GenerOS behaves better than original Linux kernel when there are more processing cores (19.6% for TPC-H using oracle database management system and 42.8% for httperf using apache web server).

关键词： Operating systems Kernel Linux Scalability Data structures computer architecture Database systems Web server Multicore processing

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Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors

Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...

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International Conference on computer and Information Technology (CIT)

作者： Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency.

关键词： Hardware Software algorithms Multicore processing computer architecture Bandwidth Scalability Moore's Law Aerospace industry computer industry Software design

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Grid Unit: A Self-Managing Building Block for Grid system

Grid Unit: A Self-Managing Building Block for Grid System

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Jianfeng Zhan Lei Wang Ming Zou Hui Wang Shuang Gao Yulei Ding Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Grid system software is inherently complex, hard to build and maintain. In this paper, we propose a self-managing building block: grid unit, which facilitates constructing grid system with higher availability and lower management overhead. We present an agent organization as autonomic management framework, and propose a self-recovering protocol to eliminate most of tough jobs from system administrator's routines. The system has been deployed on Dawning 4000A since 2004, the biggest node for China grid system. We have done extensive experiments to evaluate grid unit, and the collected log data shows the availability of a grid parallel process management service, built on the basis of grid unit, reaches 99.997%.

关键词： Availability Distributed computing computer architecture Protocols Large-scale systems Operating systems Resource management Application software Laboratories Concurrent computing

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A testability-aware low power architecture

A testability-aware low power architecture

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IEEE International SOC Conference

作者： Gang Wang Jian Wang Zi-Chu Qi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Test power consumption is becoming a major concern in low power integrated circuits (ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

关键词： Power demand computer architecture Switches Clocks Vectors Switching circuits Compaction

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