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Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors

Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...

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International Conference on computer and Information Technology (CIT)

作者： Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency.

关键词： Hardware Software algorithms Multicore processing computer architecture Bandwidth Scalability Moore's Law Aerospace industry computer industry Software design

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GenerOS: An asymmetric operating system kernel for multi-core systems

GenerOS: An asymmetric operating system kernel for multi-cor...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Qingbo Yuan Jianbo Zhao Mingyu Chen Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Compute Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424464425

Due to complex abstractions implemented over shared data structures protected by locks, conventional symmetric multithreaded operating system kernel such as Linux is hard to achieve high scalability on the emerging multi-core architectures, which integrate more and more cores on a single die. This paper presents GenerOS - a general asymmetric operating system kernel for multi-core systems. In principal, GenerOS partitions processing cores into application core, kernel core and interrupt core, each of which is dedicated to a specified function. In implementation, we conduct a delicate modification to Linux kernel and provide the same interface as Linux kernel so that GenerOS is compatible with legacy applications. The better performance of GenerOS mainly benefits from: (1) Applications run on their own cores with minimal interrupt and kernel support; (2) Every kernel service is encapsulated in to a serial process so that there will be fewer contentions than conventional symmetric kernel; (3) A slim schedule policy is used in the kernel core to support schedule between system calls with low overhead. Experiments with two typical workloads on 16-core AMD machine show that GenerOS behaves better than original Linux kernel when there are more processing cores (19.6% for TPC-H using oracle database management system and 42.8% for httperf using apache web server).

关键词： Operating systems Kernel Linux Scalability Data structures computer architecture Database systems Web server Multicore processing

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Grid Unit: A Self-Managing Building Block for Grid system

Grid Unit: A Self-Managing Building Block for Grid System

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Jianfeng Zhan Lei Wang Ming Zou Hui Wang Shuang Gao Yulei Ding Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Grid system software is inherently complex, hard to build and maintain. In this paper, we propose a self-managing building block: grid unit, which facilitates constructing grid system with higher availability and lower management overhead. We present an agent organization as autonomic management framework, and propose a self-recovering protocol to eliminate most of tough jobs from system administrator's routines. The system has been deployed on Dawning 4000A since 2004, the biggest node for China grid system. We have done extensive experiments to evaluate grid unit, and the collected log data shows the availability of a grid parallel process management service, built on the basis of grid unit, reaches 99.997%.

关键词： Availability Distributed computing computer architecture Protocols Large-scale systems Operating systems Resource management Application software Laboratories Concurrent computing

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A testability-aware low power architecture

A testability-aware low power architecture

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IEEE International SOC Conference

作者： Gang Wang Jian Wang Zi-Chu Qi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Test power consumption is becoming a major concern in low power integrated circuits (ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

关键词： Power demand computer architecture Switches Clocks Vectors Switching circuits Compaction

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Efficient binary translation system with low hardware cost

Efficient binary translation system with low hardware cost

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Weiwu Hu Qi Liu Jian Wang Songsong Cai Menghao Su Xiaoyu Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing architecture. The hardware supports for source-architecture-only functions, partial decodes and binary translation system acceleration are proposed. These hardware supports help the binary translation system to achieve high performance and simplify the design of the binary translation software. In the meantime, the hardware cost is well controlled in a certain low level. These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. Performance evaluations on RTL simulation and FPGA emulation platforms show that the proposed method can speedup most benchmark programs by nearly 10 times compared to pure software-based binary translation and achieves about 70% performance of the native program execution. The chip is fabricated in ST 65nm CMOS technology, and the physical design results show that the chip area cost is less than 5%.

关键词： Hardware Costs computer architecture Acceleration CMOS technology Software systems Virtual machining Decoding Software performance Field programmable gate arrays

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Column-based RLE in row-oriented database

Column-based RLE in row-oriented database

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International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC

作者： Mingyuan An Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (run-length encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage.

关键词： Database systems system performance Encoding Compression algorithms Costs Memory Engines Laboratories computer architecture Query processing

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A resilient on-chip router design through data path salvaging 11

A resilient on-chip router design through data path salvagin...

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Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permanent faults such as manufacturing defects, device wear-out, which hinder the correct operations of the entire system. Therefore, effective fault-tolerant techniques are essential to improve the reliability of NoCs. Prior work mainly focuses on introducing redundancies, which can't achieve satisfactory reliability and also involve large hardware overhead, especially for data path components. In this paper, we propose fine-grained data path salvaging techniques by splitting data path components, i.e., links, input buffers and crossbar into slices, instead of introducing redundancies. As long as there is one fault-free slice for each component, the router can be functional. Experimental results show that the proposed solution achieves quite high reliability with graceful performance degradation even under high fault rate.

关键词： Fault tolerant systems Redundancy Pipelines Routing Circuit faults

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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip 11

Vertical interconnects squeezing in symmetric 3D mesh Networ...

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Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs' utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant TSV footprint with negligible performance overhead.

关键词： Through-silicon vias Three dimensional displays Pipelines Routing Throughput computer architecture system-on-a-chip

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Processes scheduling on heterogeneous multi-core architecture with hardware support

Processes scheduling on heterogeneous multi-core architectur...

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IEEE International Conference on Networking, architecture and Storage

作者： Hao, Shouqing Liu, Qi Zhang, Longbing Wang, Jian Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP system, the applications should be scheduled to the proper cores by the scheduler of the operating system according to their behaviours. Besides, the last level cache (LLC) miss rate is often used as the metric to identify the application features. However, the LLC miss rate could not reflect the application behaviours accurately since the memory access delay, the most important application character is related to patterns of the memory access and many other issues. To improve the accuracy of scheduling on the heter-CMP system, this paper supplies performance counters for the LLC miss penalty to monitor application behaviours. Based on that, the latency-aware scheduling algorithm for asymmetry chip multi-processors (LA-ACMP) is proposed and implemented. Those hardware supports are implemented on the Godson-3 multi-core RTL and simulator and the LA-ACMP algorithm is integrated to the Linux kernel. The performance evaluation on those platforms shows that the LA-ACMP algorithm with LLC miss penalty outperforms the algorithm with LLC miss rate about 32.4%, and outperforms the original schedule algorithm about 18.4%. © 2011 IEEE.

关键词： Scheduling algorithms

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Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP

Snooping and Ordering Ring - An Efficient Cache Coherence Pr...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Fei Cao Zhiyong Liu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%.

关键词： Broadcasting Bandwidth Delay Multiprocessing systems Energy consumption Access protocols Laboratories Concurrent computing Distributed computing computer architecture

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